Sense Amplifier Circuit Calibration for Memory Data Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face issues with invalid data sensing due to threshold voltage mismatch between transistors and the presence of dummy cells in open bit line structures, which affect data sensing characteristics and chip size.
Innovation Solution
A bit line sense amplifier circuit with a 2-stage cascade latch and a calibration circuit that calibrates the voltage level of the bit line based on a logic threshold value, eliminating the need for a reference bit line and reducing the influence of transistor mismatches, thereby improving data sensing characteristics and eliminating dummy cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cross-coupled latch sense amplifier is used for differential pair sensing, then data sensing capability is achieved, but invalid sensing occurs due to threshold voltage mismatch between transistors
Solution Approach 1:
The patent applies preliminary action by performing offset calibration before the actual data sensing operation. The calibration circuit adjusts the bit line voltage to compensate for transistor threshold voltage mismatches in advance, ensuring accurate sensing during subsequent operations. This pre-calibration step eliminates the invalid sensing problem caused by mismatches in cross-coupled latch amplifiers.
Solution Approach 2:
The patent implements feedback through the calibration circuit that monitors and adjusts the bit line voltage based on the logic threshold value. This feedback mechanism continuously compensates for threshold voltage variations in transistors, maintaining accurate sensing conditions and preventing invalid data sensing.
2Area of stationary object
If an open bit line structure is used, then memory cell array size is reduced, but dummy cells are created that cannot be used
Solution Approach 1:
The patent changes the voltage parameter of the bit line through calibration to eliminate the need for reference bit lines. By adjusting the bit line voltage to match the logic threshold value, the system can operate with open bit line structures without creating dummy cells, thus maintaining full cell utilization while reducing array size.
3Device complexity
If a folded bit line structure is used, then sense amplifier block can be shared, but memory cell array size becomes greater
Solution Approach 1:
The patent uses parameter changes by calibrating the bit line voltage to eliminate the need for reference bit lines in folded structures. This allows the sense amplifier to share between memory cell blocks more efficiently, reducing the overall array size while maintaining the sharing capability.
4Reliability
If reference bit line is used in differential pair sensing, then sensing operation is enabled, but chip size increases
Solution Approach 1:
The patent extracts and eliminates the reference bit line from the sensing system. By using a calibration circuit that adjusts the bit line voltage to match the logic threshold value, the system can perform sensing operations without requiring a separate reference bit line, thus reducing chip size while maintaining sensing reliability.
Solution Approach 2:
The patent implements self-service by having the calibration circuit automatically adjust the bit line voltage to the appropriate logic threshold value. This self-adjusting mechanism eliminates the need for external reference bit lines, allowing the system to perform sensing operations independently without additional reference structures.
Data Source
AI summary
A sense amplifier circuit of a semiconductor memory device and a method of operating the same, in which the sense amplifier circuit includes a bit line sense amplifier connected with a bit line to sense and amplify a signal of the bit line, and a calibration circuit calibrating a voltage level of the bit line based on a logic threshold value of the bit line sense amplifier. The bit line sense amplifier senses and amplifies the signal of the bit line after the voltage level of the bit line is calibrated. The bit line sense amplifier may include a 2-stage cascade latch, which includes a first inverter having an input terminal connected with the bit line; and a second inverter which has an input terminal connected with an output terminal of the first inverter and an output terminal connected with the bit line and is enabled/disabled in response to a sensing control signal. The calibration circuit includes a switch element that is connected between the output terminal of the first inverter and the bit line and is turned on or off in response to a calibration control signal.