Sense Amplifier Capacitor for Interrupt Data Caching

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Solution Overview

Problem

Current semiconductor memory devices face challenges in efficiently managing data transfer and storage during interrupt operations without increasing the device's area, particularly in NAND flash memory systems where write operations are interrupted for read commands, leading to complexities in data handling and potential area expansion.

Innovation Solution

Incorporating a capacitor element within the sense amplifier to temporarily store data during interrupt operations, allowing for dynamic caching without increasing the number of latch circuits, thus preventing area expansion and enhancing operational efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional latch circuits are added to handle interrupt operations, then data storage capability during interrupts is improved, but device area increases

Engineering Contradiction:
Improvedata storage capabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The capacitor element that is originally part of the sense amplifier circuit is made to serve dual purposes: maintaining its original function in the sense amplifier while simultaneously acting as a temporary storage element for interrupt operations. This multi-functionality allows the circuit to handle interrupts without adding dedicated storage circuits, thus avoiding area expansion.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The sense amplifier's existing capacitor element is utilized to store data during interrupt operations, allowing the circuit to serve itself rather than requiring external or additional components. The capacitor naturally present in the sense amplifier is repurposed for data retention during interrupts, eliminating the need for separate storage infrastructure.

Inventive Principle:
Principle #25Self-service

2Productivity

If the sense amplifier structure is modified to include additional storage elements, then operational efficiency during interrupts is improved, but device complexity increases

Engineering Contradiction:
Improveoperational efficiencyVSAvoidcircuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The sense amplifier circuit is designed so that its existing capacitor element performs multiple functions: it maintains the sense amplifier's operational capability while simultaneously providing temporary data storage during interrupt operations. This eliminates the need for separate storage circuits and reduces overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The data storage function for interrupt operations is merged with the existing sense amplifier circuit rather than being implemented as a separate component. The capacitor element within the sense amplifier is combined with the interrupt handling logic, creating an integrated solution that improves operational efficiency without increasing device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables seamless interrupt operations without area expansion, improves sense amplifier functionality, and maintains data integrity by using the capacitor element as a dynamic cache, reducing the need for additional latch circuits.

Implementation Method 1

a first capacitor element (45) of which one electrode is connected to a first node (SEN) electrically connectable to the bit line

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11417401B2Semiconductor memory device
Publication Date: 2022.08.16 KIOXIA CORP
  • US11417401B2 patent drawing
  • US11417401B2 patent drawing
  • US11417401B2 patent drawing

AI summary

A semiconductor memory device includes a bit line, a first memory cell electrically connected to the bit line, and a sense amplifier connected to the bit lin. The sense amplifier includes a first capacitor element having an electrode that is connected to a first node electrically connectable to the bit line, a first transistor having a gate connected to the first node and a first end connectable to a second node, a second transistor having a first end connected to the second node and a second end connected to a third node, a second capacitor element having an electrode connected to the third node, and a latch circuit connected to the second node.