Sense Amplifier Common Node for FeRAM Current Reduction

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Solution Overview

Problem

In memory devices, especially FeRAM, sense amplifiers often consume excessive current when detecting a significant quantity of bits of one logic state, leading to increased system latency and power consumption.

Innovation Solution

Implementing a set of sense circuits that share portions of a differential amplifier, including a common node, to reduce current consumption by selectively coupling transistors and allowing current to flow only when the memory cell stores a specific logic state, thereby optimizing the sense operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sense amplifiers use separate branches for each sense circuit, then each sense amplifier can independently detect logic states, but current consumption increases significantly when detecting a significant quantity of bits of one logic state

Engineering Contradiction:
Improvesense operation reliabilityVSAvoidcurrent consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

Multiple sense circuits share a common second branch of the differential amplifier instead of each having a separate branch. This merging of resources allows the sense amplifiers to detect logic states while significantly reducing current consumption, as the common branch serves multiple circuits simultaneously rather than each circuit requiring its own dedicated current path

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The common second branch of the differential amplifier serves multiple sense circuits simultaneously, making it a universal component that performs the same function for multiple circuits. This multi-functionality reduces the overall current consumption while maintaining the ability to detect logic states across multiple memory cells

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If sense amplifiers consume excessive current, then detection capability is maintained, but system latency increases

Engineering Contradiction:
Improvelogic state detection capabilityVSAvoidsystem latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

By merging multiple sense circuits into a shared differential amplifier structure with a common second branch, the system maintains detection capability while reducing current consumption. This reduces unnecessary current draw that would otherwise increase system latency, allowing faster sense operations

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If sense amplifiers consume excessive current, then detection capability is maintained, but power consumption increases

Engineering Contradiction:
Improvelogic state detection capabilityVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

Multiple sense circuits share a common second branch of the differential amplifier, merging current paths to reduce overall power consumption. This merging maintains the ability to detect logic states accurately while significantly reducing the power required for sense operations compared to having separate branches for each sense circuit

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The common second branch provides just enough current capacity to serve multiple sense circuits simultaneously without the excessive current that would be required if each circuit had its own dedicated branch. This partial action approach reduces power consumption while maintaining sufficient detection capability

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11756602B2Sensing component with a common node
Publication Date: 2023.09.12 MICRON TECHNOLOGY INC
  • US11756602B2 patent drawing
  • US11756602B2 patent drawing
  • US11756602B2 patent drawing

AI summary

Methods, systems, and devices for sensing component with a common node are described. A set of sense circuits of a memory device may include a shared differential amplifier having a first branch for each sense circuit and a shared second branch, as well as a shared common node. A respective latch of each sense amplifier may be initialized to a second logic state, and the common node may undergo a voltage ramp to determine the state stored in the memory cell. If the memory cell stores the first logic state, the sense amplifier may couple with the common node to draw the current and switch the state of the latch to the first logic state. Alternatively, if the memory cell stores the second logic state the current may not be drawn and the state of the latch may not switch.