Sense Amplifier Contact Orientation for NAND Flash Reliability
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Solution Overview
Problem
The miniaturization of NAND flash memory cells leads to reduced bit line arrangement pitches, resulting in scaled-down sense amplifiers with insufficient contact areas, causing frequent poor contact issues due to inadequate contact resistance.
Innovation Solution
The arrangement of sense amplifiers within the width of bit lines, where the gate length direction of transistors matches the bit line direction, and the longer side of contact electrodes aligns with the bit line, ensuring secure contact areas and reducing contact failure risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If sense amplifiers are scaled down to match miniaturized memory cells, then memory device density increases, but contact area decreases leading to poor contact reliability
Solution Approach 1:
The patent reorients the contact electrode arrangement from a conventional layout to one where the longer side of contact electrodes aligns with the bit line direction. This dimensional reconfiguration allows contact electrodes to extend along the bit line, effectively increasing contact area without expanding the overall footprint in the critical width direction, thus maintaining high density while improving contact reliability
Solution Approach 2:
The patent applies different orientation configurations to different components: transistors are arranged with gate length direction matching bit line direction, while contact electrodes are positioned with their longer sides also aligned with the bit line. This localized optimization of component orientation ensures that each element contributes maximally to either density or contact reliability depending on its functional requirements
2Length of moving object
If bit line arrangement pitch is reduced for miniaturization, then memory cell density increases, but sense amplifier contact area becomes insufficient
Solution Approach 1:
The patent utilizes the length dimension along the bit line direction to compensate for the reduced pitch. By extending contact electrodes along the bit line (increasing their length in that direction), the contact area is maintained even though the pitch between bit lines has been reduced, allowing density improvement without sacrificing contact area
3Volume of moving object
If sense amplifier size is reduced to match scaled memory cells, then device miniaturization is achieved, but contact resistance increases due to insufficient contact area
Solution Approach 1:
The patent compensates for reduced sense amplifier volume by reconfiguring the contact electrode geometry. The longer side of contact electrodes is aligned with the bit line direction, extending the contact interface area along the length dimension while maintaining compact width, thereby reducing contact resistance despite the overall size reduction of the sense amplifier
Solution Approach 2:
The patent optimizes the local geometry of contact electrodes specifically, making their longer side align with the bit line direction while keeping the rest of the sense amplifier compact. This localized dimensional optimization ensures sufficient contact area for low resistance without increasing the overall sense amplifier size
Data Source
AI summary
According to an embodiment, sense amplifiers are arranged one by one within an arrangement width of k bit lines in a direction of the bit lines, and determine data stored in the memory cells, based on potentials of the respective bit lines. Transistors constituting the sense amplifier are arranged one by one within an arrangement width of the sense amplifier in the direction of the bit lines. A gate length direction of the transistors is identical to the direction of the bit lines. A longer side direction of a contact electrode connected to an active area of the transistor is identical to the direction of the bit lines.