Sense Amplifier Coupling for Reduced tRCD Delay
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Solution Overview
Problem
As clock speeds in semiconductor memory increase, the time required to charge and discharge access lines during memory access operations becomes a significant contributor to latency, particularly the minimum row address to column address delay (tRCD), which can reduce the time margin available for memory operations.
Innovation Solution
The proposed solution involves coupling internal nodes of sense amplifiers to bit lines before activating them, thereby reducing the brief discharge/charge delay period, which helps in minimizing the tRCD by avoiding additional delays associated with initial discharge/charge when activating sense amplifiers after coupling to bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sense amplifiers are activated after coupling to bit lines, then the sense amplifier can perform its sensing function, but an additional discharge/charge delay period is introduced that increases tRCD
Solution Approach 1:
The patent applies preliminary action by coupling the internal nodes of the sense amplifier to the bit lines before activating the sense amplifier. This preliminary coupling ensures that the bit lines are already connected to the internal nodes, so when the sense amplifier activates, there is no additional discharge/charge delay period. The coupling action is performed in advance to eliminate the timing delay that would otherwise occur.
2Productivity
If clock speed is increased to improve memory access speed, then productivity increases, but the time required to charge and discharge access lines becomes a larger share of the allotted time, increasing tRCD
Solution Approach 1:
By performing the coupling action before sense amplifier activation, the patent eliminates the discharge/charge delay that would otherwise consume a significant portion of the memory access time. This preliminary coupling allows the system to maintain lower tRCD values even as clock speeds increase, thereby preserving productivity gains from higher clock frequencies.
Data Source
AI summary
Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state, and a sense amplifier configured to, during a sense operation, couple a first gut node to the first digit line and couple a second gut node to a second digit line in response to an isolation signal. The sense amplifier is further configured to, after the first gut node is coupled to the first digit line and the second gut node is coupled to the second digit line, drive the first digit line to a first sense voltage of a first control signal and drive the second digit line to a second sense voltage of a second control signal based on a data state of the memory cell.