Sense Amplifier Current Mirror Latch Determinacy

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Solution Overview

Problem

Prior art sense amplifier circuits for semiconductor memory devices fail to maintain determinate and complementary voltage levels at nodes N3 and N4 during the latch operation, leading to indeterminate logic states before completing the latch operation.

Innovation Solution

Incorporation of a current mirror circuit in the sense amplifier circuit, which ensures that the logic states at opposite sides of the latch circuit remain complemented and determinate throughout the read operation by managing the voltage levels effectively through a series of transistors and control signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a prior art sense amplifier circuit is used, then the latch operation can be completed, but the voltage levels at nodes N3 and N4 become indeterminate before completing the latch operation

Engineering Contradiction:
Improvedeterminacy of logic statesVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A current mirror circuit is introduced as an intermediary component between the memory units and the latch circuit. This current mirror circuit actively manages and regulates the voltage levels at nodes N3 and N4, ensuring they remain determinate and complementary throughout the read operation, thereby resolving the indeterminate logic state problem without fundamentally altering the core latch structure

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The current mirror circuit performs preliminary action by pre-establishing and maintaining proper voltage level relationships at nodes N3 and N4 before the latch operation completes. By proactively controlling the voltage levels during the read operation, the circuit prevents the indeterminate state from occurring in the first place

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If the voltage levels at nodes N3 and N4 are allowed to float during latch operation, then the latch can operate, but the logic states become indeterminate

Engineering Contradiction:
Improvelatch operationVSAvoidlogic state determinacy
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The current mirror circuit implements feedback control by continuously monitoring and adjusting the voltage levels at nodes N3 and N4. This feedback mechanism ensures that the voltage levels remain properly regulated and complementary throughout the latch operation, maintaining both ease of operation and logic state determinacy simultaneously

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The current mirror circuit ensures that the voltage levels at the latch circuit terminals are consistently complementary and determinate, enhancing the reliability of the read operation in semiconductor memory devices.

Implementation Method 1

Incorporation of a current mirror circuit in the sense amplifier circuit, which ensures that the logic states at opposite sides of the latch circuit remain complemented and determinate throughout the read operation by managing the voltage levels effectively through a series of transistors and control signals

Methodology Applied
Scientific EffectCurrent mirror:

Data Source

PatentUS7663928B2Sense amplifier circuit having current mirror architecture
Publication Date: 2010.02.16 EMEMORY TECH INC
  • US7663928B2 patent drawing
  • US7663928B2 patent drawing
  • US7663928B2 patent drawing

AI summary

A sense amplifier circuit for use in a semiconductor memory device has complemented logic states at opposite sides of the latch circuit in the sense amplifier circuit determinate all the time in operation. The sense amplifier circuit takes advantage of a current mirror circuit for ascending or descending a voltage level at the gate of a transistor by charge accumulation or charge dissipation, which turns on or off the transistor so as to control the logic states at opposite sides of the latch circuit in the sense amplifier circuit.