Four-Block Sense Amplifier for Accurate Four-Quadrant Current Sensing
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Solution Overview
Problem
Current load sense amplifier circuits face challenges in accurately combining four-quadrant signals from input-voltage-terminals into a single differential voltage signal, particularly in Class-D output stages, which affects current sensing accuracy and linearity in audio amplifiers.
Innovation Solution
A sense amplifier circuit comprising four amplification blocks with specific transistor configurations and bias voltage sources, allowing for the combination of four-quadrant signals into a single differential voltage signal, enhancing current sensing accuracy and linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional sense amplifier circuits are used to combine four-quadrant signals, then the circuit structure is relatively simple, but the current sensing accuracy and linearity deteriorate
Solution Approach 1:
The sense amplifier circuit is divided into four separate amplification blocks, each handling one quadrant of the signal. This segmentation allows each block to be optimized for specific signal characteristics while maintaining overall accuracy and linearity in the combined output.
Solution Approach 2:
Each amplification block uses specifically configured transistors (PMOS for first and third blocks, NMOS for second and fourth blocks) and dedicated bias voltage sources tailored to their respective signal quadrants. This local optimization of component characteristics improves the overall measurement precision without requiring complete redesign of the entire circuit.
2Stability of the object's composition
If four-quadrant signals are combined into a single differential voltage signal, then the current sensing linearity improves, but the device complexity increases
Solution Approach 1:
The circuit merges four separate quadrantal signals into a single differential voltage output signal representing the total load current. This combining process, achieved through the coordinated operation of four amplification blocks with properly configured transistors and bias sources, maintains signal linearity while consolidating the output for easier processing.
Solution Approach 2:
The amplification blocks use asymmetric transistor configurations (PMOS vs NMOS) and different bias voltage sources (first-bias-voltage-source vs second-bias-voltage-source) optimized for their respective signal quadrants. This asymmetric design allows each block to handle its specific signal range optimally, improving overall linearity when combined.
Data Source
AI summary
A sense amplifier circuit comprising a first-, second-, third- and fourth-amplification-blocks, each amplification-block comprising: an amplification-block-transistor comprising and an amplification-block-resistor. The amplification-block-transistor includes: a first-conduction-channel-terminal, a second-conduction-channel-terminal that is connected to an amplification-block-output-node, and a control-terminal that is connected to an amplification-block-control-node. The sense amplifier circuit also comprises: an amplification-block-resistor connected in series between an amplification-block-input-node and the first-conduction-channel-terminal; a first-bias-voltage-source connected to the amplification-block-control-nodes of the first- and third-amplification-blocks, a second-bias-voltage-source connected to the amplification-block-control-nodes of the second- and fourth-amplification-blocks. The sense amplifier circuit also comprises: a first-common-mode-voltage-resistor connected in series between a first-sensed-output-terminal and a common-mode-voltage-node; and a second-common-mode-voltage-resistor connected in series between a second-sensed-output-terminal and the common-mode-voltage-node.