Sense Amplifier Data Latch Segmentation for Flag Read
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Solution Overview
Problem
In binary data storage systems like SLC, the existing sense amplifiers with a single data latch cannot perform flag data read operations without destroying the write data, due to the lack of adequate measures in the write command sequence.
Innovation Solution
A semiconductor memory device with a sense amplifier circuit that includes multiple sense amplifiers, each with a data latch, allows for flag data read during data write by transferring read flag data to the latch for the flag data region and rewriting the write data in the ordinary data region, using a write back circuit for logical operations to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single data latch is used in the sense amplifier for SLC systems, then device complexity is reduced, but flag data read operations destroy write data
Solution Approach 1:
The patent segments the data latch into two independent latches: a first data latch for storing write data and a second data latch for storing flag data. This segmentation allows both types of data to be retained simultaneously without interference, resolving the contradiction between simple structure and data integrity.
Solution Approach 2:
The patent introduces a control signal mechanism as an intermediary to manage data retention selectively. The control signal determines whether to retain or overwrite data in each latch based on the operation type (write or flag read), enabling the single-latch structure to function reliably for both operations.
2Reliability
If multiple data latches are provided in the sense amplifier, then flag data can be read without destroying write data, but device complexity increases
Solution Approach 1:
The patent divides the data storage function into two separate latches within the sense amplifier: one dedicated to write data and another to flag data. This segmentation enables simultaneous retention of both data types, achieving reliable flag data read operations without requiring external storage mechanisms.
Solution Approach 2:
The sense amplifier is designed with multi-functionality by incorporating both write data retention and flag data read capabilities within a single integrated structure. The dual-latch configuration allows the sense amplifier to perform multiple functions (write operations and flag reads) without requiring separate external storage elements.
3Productivity
If flag data read operation is performed during write operation, then write time is reduced, but write data is destroyed in simple sense amplifiers
Solution Approach 1:
The patent performs preliminary action by loading write data into the first data latch before the write operation begins. This allows the flag data read operation to proceed simultaneously during the write process without requiring additional time, as the write data is already securely stored in the dedicated latch.
Solution Approach 2:
The patent enables continuous operation by allowing the flag data read and write operations to proceed simultaneously without interruption. The dual-latch structure ensures that both operations can occur in parallel, maintaining continuous useful action and maximizing productivity while preserving data integrity.
Data Source
AI summary
A semiconductor memory device, in which flag data read of a flag data region is performed during data write, comprises: a nonvolatile memory cell array having an ordinary data region and the flag data region allocated to a one page range in which read and write are simultaneously performed; and a one page amount of sense amplifiers, each of the sense amplifiers comprising a data latch for retaining write data. During read of the flag data by the sense amplifier circuit, in the case of one of the sense amplifiers corresponding to the flag data region, read flag data is transferred to the data latch. In the case of one of the sense amplifiers corresponding to the ordinary data region, write data retained by the data latch is rewritten regardless of read cell data.