Sense Amplifier Delay Chain Voltage Offset

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current memory technologies face challenges with analog sense amplifiers due to voltage offsetting caused by transistor mismatch and digital sense amplifiers have low operation speed.

Innovation Solution

A sense amplifier design utilizing two delay chains connected to bit lines and complementary bit lines, converting voltage differences into phase delays to determine which voltage is higher, thereby minimizing voltage offsetting and enhancing operation speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If analog sense amplifier is used, then operation speed is fast, but voltage offsetting occurs due to transistor mismatch

Engineering Contradiction:
Improveoperation speedVSAvoidvoltage measurement accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent replaces the traditional analog voltage comparison mechanism with a digital delay-based detection mechanism. Instead of directly comparing voltages using analog circuits susceptible to mismatch, the invention converts voltage information into time delay information through delay chains, which are then processed digitally to determine which bit line has the higher voltage. This substitution eliminates the voltage offsetting problem inherent in analog differential amplifiers.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If digital sense amplifier is used, then voltage offsetting is reduced, but operation speed becomes slow due to full swing operation requirement

Engineering Contradiction:
Improvevoltage measurement accuracyVSAvoidoperation speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent employs partial action by using only a portion of the available voltage swing to generate the delay signal, rather than requiring full swing operation. The delay chains process voltage differences with partial swing, and the phase detection circuit determines the result based on phase relationships rather than complete voltage transitions. This approach maintains the accuracy benefits of digital detection while achieving faster operation speeds by reducing the required voltage swing amplitude.

Inventive Principle:
Principle #16Partial or excessive action

3Ease of operation

If voltage values are directly compared, then determination is straightforward, but manufacturing mismatch causes offset errors

Engineering Contradiction:
Improvevoltage comparison simplicityVSAvoidvoltage comparison accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent introduces delay chains as intermediary elements between the voltage signals and the comparison operation. Instead of directly comparing voltages, the invention first converts voltage information into time delay information through the delay chains, which act as mediators. The phase detection circuit then compares the delayed signals, effectively using time delay as an intermediary representation of voltage magnitude. This intermediary approach preserves the simplicity of comparison while eliminating manufacturing mismatch errors.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8588020B2Sense amplifier and method for determining values of voltages on bit-line pair
Publication Date: 2013.11.19 MARLIN SEMICON LTD
  • US8588020B2 patent drawing
  • US8588020B2 patent drawing
  • US8588020B2 patent drawing

AI summary

A sense amplifier and a method for determining the values of the voltages on a bit-line pair are provided. The sense amplifier comprises a first delay chain and a second delay chain. The first delay chain is electrically connected to a bit line and configured for receiving a clock signal and a first voltage on the bit line, so as to delay the clock signal according to the first voltage and to generate a first delay signal accordingly. The second delay chain is electrically connected to a complementary bit line and configured for receiving the clock signal and a second voltage on the complementary bit line, so as to delay the clock signal according to the second voltage and to generate a second delay signal accordingly.