Semi-shared sense amplifier discharge circuit for memory read speed
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Solution Overview
Problem
Multi-bank semiconductor memory architectures face challenges with capacitive loading on global read lines, which slows down memory readout speed due to shared sense amplifiers and increased transistor size, and non-shared architectures require more sense amplifiers, increasing integrated circuit area and power consumption.
Innovation Solution
A semi-shared architecture where each bank has its own sense amplifier, with a discharge circuit that includes a single N-channel pulldown transistor to minimize capacitive loading on global read lines, and a logic gate to control discharging based on the logical OR condition of sense amplifier outputs, allowing differential global read lines to reduce transistor count on read lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If shared sense amplifier architecture is used, then the number of sense amplifiers is reduced and integrated circuit area is reduced, but capacitive loading on global read line increases and memory readout speed decreases
Solution Approach 1:
The invention segments the sense amplifier functionality by separating the sense amplifier core from the output driver stage. Each bank has its own dedicated sense amplifier that drives a shared global read line, but the driving action is segmented in time through controlled enabling. This allows multiple sense amplifiers to share the global read line without simultaneous capacitive loading conflicts, thereby maintaining high readout speed while reducing the total number of sense amplifiers compared to fully non-shared architectures.
2Speed
If P-channel transistors are added to isolate device junction capacitance, then capacitive loading on sense amplifier input leads is reduced, but memory readout speed decreases due to transistors in data output signal path
Solution Approach 1:
The invention extracts the isolating function from the data output signal path by removing P-channel transistors from between the sense amplifier and global read line. Instead, isolation is achieved through the enabling mechanism that controls when sense amplifiers drive the shared global read line. This extraction eliminates the speed penalty associated with P-channel transistors in the signal path while still providing necessary isolation through temporal separation of driving actions.
3Speed
If non-shared sense amplifier architecture is used, then memory readout speed is improved, but the number of sense amplifiers increases and integrated circuit area increases
Solution Approach 1:
The invention merges multiple sense amplifier outputs onto a single shared global read line through controlled enabling. Each bank has its own sense amplifier (maintaining speed performance), but their outputs are combined on the shared global read line with only one enabled at a time. This merging approach reduces the total number of sense amplifiers and integrated circuit area while preserving the speed benefits of dedicated sense amplifiers through temporal separation.
Data Source
AI summary
A memory includes a global read line and a plurality of banks. For each bank, the memory includes a sense amplifier. A discharge circuit discharges the global read line if any one of a plurality of the sense amplifiers is enabled and is outputting a signal having a first digital logic value onto an input lead of the discharge circuit. In this way, the sense amplifiers share the discharge circuit. In one example, the memory includes a pair of differential read lines that are precharged to begin a read operation. After precharging, if either of two sense amplifiers is enabled and outputting the first digital logic value, then a first discharge circuit discharges a first of the global read lines. If either of two sense amplifiers is enabled and outputting the second digital logic value, then a second discharge circuit discharges a second of the global read lines.