Sense Amplifier Discharge Timing for NAND Flash Memory
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Solution Overview
Problem
Conventional Quick Pass Write (QPW) techniques in NAND flash memory require multiple read operations to detect data during and after sense node discharge, leading to potential data detection errors due to changing sense node voltages, which can result in incorrect data transfer to latch circuits during verify read stages.
Innovation Solution
The semiconductor storage device modifies the discharge period of sense nodes based on data detected at the verify read stage in a previous write loop, allowing for accurate data detection without changing the word line voltage, thus reducing setup time and improving data transfer accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is detected during discharge of sense nodes to reduce setup time, then setup time for word lines is reduced, but data detection accuracy deteriorates due to changing sense node voltages
Solution Approach 1:
The patent applies preliminary action by performing the data detection operation after the sense node discharge is completed, rather than during the discharge process. The verify read operation is timed to occur after the discharge period, ensuring that the sense node voltage has stabilized before data detection begins. This eliminates the problem of voltage changes during detection while still maintaining efficient timing by not requiring additional setup time for word lines.
2Adaptability or versatility
If data is detected during discharge of sense nodes, then threshold voltage can be detected at multiple levels, but data transfer accuracy to latch circuit deteriorates due to sense transistor conduction state switching
Solution Approach 1:
The patent ensures that the data detection operation is performed after the sense node discharge has completed, so that the sense transistor conduction state is stable before data capture begins. The timing is arranged so that the verify read occurs in the subsequent write loop after discharge, preventing any switching of conduction state during the critical data capture period by the latch circuit.
3Measurement precision
If discharge period of sense nodes is extended to improve data detection accuracy, then data capture accuracy improves, but write sequence duration increases
Solution Approach 1:
The patent maintains continuous useful action by overlapping the discharge period with the preparation for the next verify read operation. The discharge of sense nodes occurs during the write loop, and the verify read is performed in the subsequent write loop without requiring additional idle time. This continuous operation ensures data capture accuracy while preventing extension of the overall write sequence duration.
Data Source
AI summary
A memory includes memory cells and a sense amplifier including a sense node that transmits a voltage according to a current flowing in one of the memory cells and detects logic of data based on the voltage of the sense node. A write sequence of writing data in a selected cell is performed by repeating write loops each including a write stage of writing data in the selected cell and a verify read stage of verifying that the data has been written in the selected cell by performing discharge from the sense node through the selected cell. The sense amplifier changes, according to a logic of data detected at the verify read stage in a first write loop, a period of discharge from the sense node to the selected cell at the verify read stage in a second write loop following the first write loop.