Offset-Canceling Sense Amplifier With Double Sensing Margin

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Solution Overview

Problem

Conventional sense amplifiers in semiconductor memory chips face degradation in sensing margin due to technology scaling, supply voltage decrease, and process variations, leading to poor performance and manufacturing issues, which are not adequately addressed by existing solutions such as tighter MTJ resistance distributions or offset-canceling circuits.

Innovation Solution

A current sense amplifier circuit design that includes degeneration transistors, load transistors, capacitors, and switch configurations to create a double sensing margin structure with strong positive feedback, allowing for improved sensing margins and speed by insensitivity to supply voltage noise and process variations, and eliminating the need for multi-stage sensing operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional sense amplifier circuits are used with technology scaling, then device complexity is reduced, but sensing margin degrades due to supply voltage decrease and process variation

Engineering Contradiction:
Improvesense amplifier circuit complexityVSAvoidsensing margin
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The sense amplifier is segmented into multiple functional blocks: a first sense amplifier for sensing bitline signals, a second sense amplifier for sensing dummy bitline signals, and a differential amplifier for comparing the two signals. This segmentation allows independent optimization of each block to maintain sensing margin while managing complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A dummy bitline and second sense amplifier are introduced as intermediary elements. The dummy bitline carries a reference signal that mediates the comparison process, allowing the differential amplifier to accurately determine data bits even in the presence of supply voltage noise and process variations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If offset-canceling circuits are used to overcome sensing margin degradation, then sensing margin is improved, but speed degrades due to multi-stage sensing operation

Engineering Contradiction:
Improvesensing marginVSAvoidsensing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The dummy bitline is pre-charged to a reference voltage level before the sensing operation begins. This preliminary action establishes a stable reference that eliminates the need for multi-stage offset cancellation, allowing single-stage high-speed sensing while maintaining accurate sensing margin.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If tighter MTJ resistance distributions are used, then sensing margin is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvesensing marginVSAvoidMTJ resistance distribution control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

Instead of relying on tight control of memory cell MTJ resistance distributions, the invention creates a copied reference signal through the dummy bitline and second sense amplifier. This copying approach transfers the reference level to the sensing path, maintaining sensing margin without imposing stringent manufacturing precision requirements on the memory cells themselves.

Inventive Principle:
Principle #26Copying

Data Source

PatentEP3281201B1System, apparatus, and method for sense amplifiers
Publication Date: 2021.07.14 QUALCOMM INC
  • EP3281201B1 patent drawingFigure 1
  • EP3281201B1 patent drawingFigure 2
  • EP3281201B1 patent drawingFigure 3

AI summary

An offset cancelling sense amplifier according to some examples of the disclosure may use a double sensing margin structure and positive feedback to achieve better performance characteristics and read stability without a multistage operation. For example, a sense amplifier may include a second pair of sensing switches cross coupled in parallel with a first pair of sensing switches and a pair of degeneration transistors coupled in line before a pair of load transistors.