Sense Amplifier Double Read Forecasting for Semiconductor Storage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current semiconductor storage devices face challenges in improving the speed of read operations due to manufacturing variances and increased bit line capacity, leading to erroneous data sensing and prolonged waiting times for voltage and current stabilization.

Innovation Solution

The implementation of a double read method and forecasting sense technique, where bit lines are locked out and precharged, allowing for two sense operations to forecast the final bit line potential, enabling accurate data reading before the stabilization time is fully reached, thus reducing operation time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the bit line capacity is increased to support more memory cells, then the storage density is improved, but the time required for voltage and current stabilization is prolonged

Engineering Contradiction:
Improvestorage densityVSAvoidstabilization time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing a first sense operation before the bit line potential is fully stabilized, and using the result to forecast the final sensed value. This allows the system to obtain accurate read data without waiting for complete stabilization, thereby reducing the effective read time while maintaining accuracy despite increased bit line capacity

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the read operation time is reduced to improve speed, then the productivity is improved, but the accuracy of data sensing deteriorates due to manufacturing variances and bit line fluctuations

Engineering Contradiction:
Improveread operation speedVSAvoiddata sensing accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent implements feedback by performing multiple sense operations (first and second sense operations) and using the results to forecast the final sensed value. The system continuously monitors bit line potential changes and adjusts the reading process based on observed trends, ensuring accurate data retrieval even when read time is reduced. This feedback mechanism compensates for manufacturing variances and bit line fluctuations

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies partial action by performing sense operations at intermediate time points before full stabilization occurs. Instead of waiting for complete stabilization, the system performs sense operations at optimized time points and uses forecasting to determine the final value, achieving both speed and accuracy by doing just enough sensing rather than waiting for complete stabilization

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If the stabilization waiting time is extended to ensure accurate sensing, then the measurement precision is improved, but the operation speed is reduced

Engineering Contradiction:
Improvesensing accuracyVSAvoidoperation speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent performs preliminary sense operations at optimized time points before full stabilization occurs. By forecasting the final sensed value based on intermediate measurements and bit line potential trends, the system achieves accurate sensing without extending the full stabilization waiting time, thus maintaining both precision and speed

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9087597B2Semiconductor storage
Publication Date: 2015.07.21 KIOXIA CORP
  • US9087597B2 patent drawing
  • US9087597B2 patent drawing
  • US9087597B2 patent drawing

AI summary

A semiconductor storage includes memory cells, a bit line, and a sense amplifier having a first transistor that controls precharging of the bit line, a second transistor that controls charging of a first node, a third transistor that controls connection of the bit line to the first node, a fourth transistor that controls connection of the first node to a second node, a fifth transistor that controls connection of the first node to a third node, and a sixth transistor that is controlled to sense a potential of the third node. The controller controls the first through sixth transistors of data to perform a read operation based on the potential of the third node.