Sense Amplifier Voltage Control for DRAM Retention Improvement
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Solution Overview
Problem
Traditional DRAM architectures face challenges in maintaining data integrity over extended periods due to capacitor leakage, leading to increased power consumption and reduced efficiency.
Innovation Solution
Reducing the voltage across memory cells and increasing cell capacitance by optimizing sense amplifier power supply levels, combined with enhanced sense amplifier architectures, to minimize leakage and enhance retention time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DRAM architectures use standard capacitor voltage levels, then read/write operations function correctly, but leakage current increases and retention time decreases
Solution Approach 1:
The patent applies parameter changes by reducing the voltage level across the storage capacitor from traditional 1V to approximately 0.5V-0.6V. This voltage reduction directly decreases leakage current through the capacitor, thereby extending retention time from typical values to over 60 milliseconds while maintaining data integrity through the enhanced sense amplifier compensation mechanisms
2Duration of action of stationary object
If capacitor voltage is reduced to extend retention time, then leakage current decreases, but sense amplifier detection capability deteriorates
Solution Approach 1:
The patent implements preliminary action through precharge operations that boost the bit line voltage to higher levels (e.g., 0.7V-0.8V) before actual read operations. This pre-charging compensates for the reduced capacitor voltage, ensuring that the sense amplifier receives sufficient signal strength for reliable detection while the capacitor operates at lower voltage for extended retention
Solution Approach 2:
The patent employs dynamic voltage adjustment where the sense amplifier supply voltage and bit line precharge voltage are adaptively modified based on the reduced capacitor voltage. The system dynamically balances the reduced storage voltage with enhanced sensing voltages to maintain detection precision despite operating at lower energy levels
3Reliability
If frequent refresh operations are performed to maintain data integrity, then data reliability is maintained, but power consumption increases
Solution Approach 1:
The patent fundamentally changes the voltage parameter of the storage capacitor to approximately half of traditional levels. This parameter change reduces leakage current by a factor of 4-5 times (following the square law relationship), enabling retention time extension to over 60 milliseconds and reducing refresh frequency requirements, thereby cutting power consumption for refresh operations significantly while maintaining data integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases memory cell retention time and reduces power consumption, achieving improved data integrity and efficiency in DRAM systems.
Implementation Method 1
a sense amplifier coupled to the data line and configured to detect a voltage change on the data line in response to the charge transfer
Implementation Method 2
a storage capacitor coupled to the data line through a selector and configured to store a charge representative of a binary value
Data Source
AI summary
Systems and methods for sense amplifier power reduction are disclosed including controlling a supply voltage to a sense amplifier through different periods of operation, including providing a first supply voltage to the sense amplifier during an activation period and a second supply voltage to the sense amplifier lower than the first supply voltage during a precharge period to reduce power consumption of the sense amplifier. A voltage supply to a memory cell can be limited to the second supply during the precharge period to reduce a potential voltage stored at the memory cell, increasing memory cell retention.