Sense Amplifier ECC Placement in DRAM Arrays
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Solution Overview
Problem
Existing DRAM technologies face challenges in miniaturization and integration density due to increased device variation and voltage mismatch, leading to area penalties and power consumption issues when implementing error correction codes, particularly with the use of 3-bit check bits for 4-bit data, which are difficult to integrate near sense amplifiers without significant area and delay penalties.
Innovation Solution
The semiconductor memory device incorporates error correction code circuits near sense amplifier arrays, allowing for efficient error correction with reduced power consumption and area penalties by using a 9-bit check bit for 64-bit data, enabling closer placement of sense amplifiers and error correction code circuits, and providing redundant memory arrays with exclusive error correction code circuits to facilitate efficient layout and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If error correction code circuits are disposed far from sense amplifier arrays, then wiring complexity is reduced, but power consumption increases and delay time increases
Solution Approach 1:
The patent changes the spatial arrangement from conventional separate placement to integrated placement where ECC circuits are disposed within the same array structure as sense amplifiers, effectively using the vertical/dimensional space of the memory array to house ECC circuits. This dimensional reorganization reduces wiring distance without significantly increasing planar wiring complexity.
Solution Approach 2:
The patent merges the ECC circuits with the sense amplifier array by disposing ECC circuits for different memory banks within the same array structure. This consolidation allows shared resources and reduces the overall distance between sense amplifiers and their corresponding ECC circuits, thereby reducing power consumption while maintaining manageable wiring complexity.
2Reliability
If check bit ratio is increased to 3 bits for 4 bits data, then error correction capability is improved, but area penalty increases by 75%
Solution Approach 1:
Instead of applying full 3-bit ECC to all data bits uniformly, the patent uses different check bit ratios for different memory banks or regions. Some banks use 3-bit ECC while others use 1-bit or 2-bit ECC, allowing the system to achieve adequate error correction capability for critical regions while minimizing area penalty in less critical regions.
Solution Approach 2:
The patent applies error correction with varying check bit ratios to different local regions or banks of the memory array. Critical memory banks that require higher reliability use 3-bit ECC, while less critical banks use reduced ECC schemes, thereby optimizing the balance between error correction capability and area utilization across different parts of the memory device.
3Area of stationary object
If check bit ratio is reduced to 8 bits for 64 bits data, then area penalty is reduced to 10%, but error correction capability is weakened
Solution Approach 1:
The patent segments the 64-bit data into multiple smaller groups, each protected by its own ECC circuit with appropriate check bits. Instead of using a single 8-bit ECC for all 64 bits, the data is divided into groups (e.g., four 16-bit groups with 2-bit ECC each, or eight 8-bit groups with 1-bit ECC each), maintaining area efficiency while providing distributed error correction coverage.
Solution Approach 2:
The patent changes the ECC parameters (check bit ratio, group size, code type) to optimize the balance between area and reliability. By adjusting these parameters based on specific application requirements and memory bank characteristics, the system achieves adequate error correction capability with minimal area penalty, rather than using a fixed high-ratio ECC scheme.
4Use of energy by moving object
If sense amplifiers and ECC circuits are placed close together, then power consumption and delay are reduced, but area for direct peripheral circuits increases
Solution Approach 1:
The patent utilizes the vertical dimension and the space between memory cell rows to dispose ECC circuits, rather than allocating additional planar area in the peripheral region. By embedding ECC circuits within the array structure and using inter-row spaces, the design achieves close proximity between sense amplifiers and ECC circuits without significantly increasing the area of direct peripheral circuits.
Solution Approach 2:
The patent nests ECC circuits within the memory array structure itself, placing them in the spaces between memory cell rows or in shared regions. This nesting approach allows ECC circuits to be physically close to sense amplifiers for reduced power and delay, while the overall footprint remains contained within the existing array boundaries without requiring additional peripheral circuit area.
Data Source
AI summary
A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.