Two-Stage Sense Amplifier for DRAM Edge Sub-Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In dynamic random access memory (DRAM) systems, the shrinking process leads to decreased sense signal margin due to Vth mismatch between paired transistors in sense amplifiers, and the requirement for high-precision bit line capacitance matching limits the use of edge sub-arrays, resulting in unavailable memory cells.
Innovation Solution
A two-stage sense amplification device is introduced, where the first stage amplifiers enhance small signals on bit lines, and a differential second stage amplifier further amplifies these signals, eliminating the need for high-precision capacitance matching and allowing full utilization of edge sub-arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If process shrinkage is implemented to increase memory density, then memory capacity is improved, but sense signal margin decreases due to Vth mismatch between paired transistors
Solution Approach 1:
The sense amplifier is divided into two independent stages: a first sense amplifier stage and a second sense amplifier stage. Each stage independently amplifies the sense signal, with the first stage providing initial amplification and the second stage providing further amplification. This segmentation allows each stage to be optimized independently, maintaining sufficient sense signal margin even as process shrinkage reduces individual transistor matching precision.
Solution Approach 2:
The first sense amplifier acts as an intermediary between the bit line and the second sense amplifier. It converts the small sense signal from the bit line into a larger intermediate signal that is then fed to the second sense amplifier for further amplification. This intermediate amplification step ensures that the final output has sufficient margin despite process variations.
2Measurement precision
If high-precision bit line capacitance matching is required for accurate differential sensing, then sensing precision is improved, but edge sub-arrays require dummy bit lines and dummy memory cells making them unavailable
Solution Approach 1:
The sensing function is segmented into two independent amplifier stages rather than requiring a single high-precision differential amplifier. This segmentation removes the requirement for high-precision bit line capacitance matching, allowing edge sub-arrays to use all their memory cells without dummy structures.
Solution Approach 2:
The requirement for high-precision capacitance matching is extracted and removed from the system by using two independent sense amplifiers instead of one differential amplifier. The first sense amplifier converts the differential signal to a single-ended signal, and the second sense amplifier processes this converted signal, eliminating the need for precise capacitance matching between bit lines.
Data Source
AI summary
A sense amplification device is provided. The sense amplification device includes a first sense amplifier, a second sense amplifier, and a third sense amplifier. An input terminal of the first sense amplifier is coupled to a first bit line. An input terminal of the second sense amplifier is coupled to a second bit line. The third sense amplifier has a differential input pair and a differential output pair, wherein a first input terminal of the differential input pair is coupled to an output terminal of the first sense amplifier, a second input terminal of the differential input pair is coupled to an output terminal of the second sense amplifier, a first output terminal of the differential output pair is coupled to the input terminal of the first sense amplifier, and a second output terminal of the differential output pair is coupled to the input terminal of the second sense amplifier.