Sense Amplifier Latch Timing for Stable NAND Flash Read-Write
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Solution Overview
Problem
Existing NAND flash memory devices face challenges in efficiently reading and writing data due to limitations in the sense amplifier module's operation, particularly in handling the inversion and storage of data within latch circuits.
Innovation Solution
The implementation of a first latch circuit with a first inverter and a second inverter, where data is stored by setting them to a driven state, read from the first node to a bus by setting them to an undriven state, and then writing the inverted data to the first node by re-driving the second inverter, optimizing data handling within the sense amplifier module.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is read from the first node to the bus by setting the latch circuit to an undriven state, then data reading is enabled, but the latch circuit cannot maintain data storage stability
Solution Approach 1:
The latch circuit dynamically switches between driven and undriven states based on operational requirements. During read operations, the circuit transitions to an undriven state to enable data output to the bus, while during write operations, it returns to a driven state to maintain data storage stability. This dynamic state change allows the circuit to adapt its characteristics to different operational phases.
2Productivity
If the second inverter is driven immediately after writing data to the first node, then data inversion is completed, but data accuracy may be compromised due to premature inversion
Solution Approach 1:
The patent implements a timing mechanism where the second inverter is configured to drive data inversion only after a predetermined period following the write operation. This preliminary waiting period ensures that the data has been properly stabilized in the first node before inversion begins, preventing premature inversion that could compromise data accuracy. The timing control acts as a buffer to ensure proper data settling.
3Reliability
If the latch circuit continuously maintains a driven state for data storage, then data storage stability is improved, but data reading and inversion operations become less efficient
Solution Approach 1:
The latch circuit employs periodic switching between driven and undriven states according to the operational requirements. Rather than maintaining a continuous driven state, the circuit periodically transitions to an undriven state during read operations and back to a driven state during write operations. This periodic action pattern optimizes both data storage stability and operational efficiency by allowing the circuit to assume the appropriate state for each operational phase.
Data Source
AI summary
In general, according to one embodiment, an operation method using a first latch circuit including: first and second inverters each includes an input terminal coupled to first and second nodes respectively, and an output terminal coupled to the second and first nodes, respectively, the operation method comprising: storing first and second data in the first and second node by setting the first and second inverters to a driven state, wherein the second data is inverted data of the first data; reading the first data from the first node to a bus coupled to the first latch circuit by setting the first and second inverters to an undriven state; writing the first data based on the second data to the first node from which the first data is read by setting the first inverter to the driven state; and driving the second inverter after the first data is written.