Sense Amplifier Layout for 3D Stacked Semiconductor Memory
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Solution Overview
Problem
The miniaturization of semiconductor memory devices is hindered by the difficulty in reducing the design rule for memory cell structures, particularly in pillar structures, which leads to inefficient circuit layout and wasted space in the memory cell array.
Innovation Solution
The semiconductor memory device employs a configuration where sense amplifiers are arranged with a reduced pitch, allowing fewer sense amplifiers in the column direction and optimizing the layout to reduce the area occupied by sense amplifiers, thereby efficiently utilizing space and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the design rule is reduced to miniaturize the semiconductor memory device, then the device size is reduced, but the memory cell array structure becomes difficult to miniaturize and circuit layout efficiency deteriorates
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked structure. Memory cell blocks are arranged in multiple layers stacked vertically, with bit line groups extending in the first direction and sense amplifiers arranged in the second direction perpendicular to the bit lines. This vertical stacking enables efficient space utilization while maintaining circuit layout efficiency despite reduced design rules.
2Reliability
If sense amplifiers are arranged with conventional pitch, then sufficient signal amplification is achieved, but the area occupied by sense amplifiers increases and space utilization deteriorates
Solution Approach 1:
The patent merges multiple sense amplifiers into a shared configuration where sense amplifiers serve multiple bit line groups. Specifically, sense amplifiers are arranged such that they can service adjacent bit line groups, reducing the total number of sense amplifiers needed while maintaining adequate signal amplification capability through the shared architecture.
Solution Approach 2:
Each sense amplifier is designed to perform multiple functions by serving multiple bit line groups. The sense amplifiers are positioned and configured to amplify signals from different bit line groups sequentially or in parallel, making them universal components that reduce overall area occupation while maintaining reliability.
3Measurement precision
If more sense amplifiers are arranged to improve signal detection, then detection capability is enhanced, but the device area increases and parasitic capacitance increases
Solution Approach 1:
Multiple bit line groups are merged to share common sense amplifiers, reducing the total number of sense amplifiers in the device. This merging approach maintains signal detection capability through the shared amplification resources while reducing parasitic capacitance by eliminating redundant sense amplifier components and their associated wiring.
Solution Approach 2:
The patent arranges sense amplifiers in a vertical stacking configuration across multiple layers, utilizing the third dimension to provide sufficient signal detection capability without increasing the planar footprint. This vertical arrangement reduces parasitic capacitance by minimizing the horizontal wiring length and component density on any single layer.
Data Source
AI summary
A semiconductor memory device comprises: a semiconductor substrate; a memory cell array provided above the semiconductor substrate and including a plurality of memory cells that are stacked; a plurality of bit lines connected electrically to the plurality of memory cells; and a plurality of sense amplifiers connected to the bit lines via bit line connection lines. The bit line connection lines have every adjacent N lines (where N is an integer of 2 or more) as one group. The sense amplifiers are arranged in a number smaller than N in a first direction that the bit line connection lines extend. An M number of the sense amplifiers are arranged in a width of a P number of groups in a second direction intersecting the first direction. The M number being larger than the P number.