Sense Amplifier Latch with Rail-to-Rail Input and Low-Voltage Sensing
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Solution Overview
Problem
Traditional Sense Amplifier Latches (SALs) perform poorly at low operating supply voltages, failing to sense input signals relative to a fixed voltage reference and exhibiting high clock-to-output delays, making them incompatible for low voltage and high-speed input-output links.
Innovation Solution
A low power Sense Amplifier Latch with rail-to-rail Input Common Mode Range (ICMR) is developed, comprising an input sensing stage with complementary devices, a decision making circuit that pre-charges nodes to determine logic levels, and a power management circuit that disables the input sensing stage during the evaluation phase to save power, operating in pre-charge, evaluation, and latch phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SAL is used, then结构简单 (structure is simple), but it fails to sense input signal at low operating voltage below 1V
Solution Approach 1:
The patent implements dynamic switching between n-type and p-type input sensing pairs based on the input common mode voltage level. When input voltage is in the lower range, the n-type pair is activated; when input voltage is in the higher range, the p-type pair is activated. This dynamic adaptation enables the SAL to sense input signals across the full rail-to-rail voltage range (0V to VDD) while maintaining reliable operation at low voltages below 1V.
Solution Approach 2:
The patent changes the operational parameters of the input sensing stage by using complementary n-type and p-type device pairs with different threshold voltages and transconductance characteristics. The control circuit dynamically adjusts which pair is active based on the input common mode voltage, effectively changing the sensing parameter to match the operating voltage range and enable rail-to-rail input common mode range.
2Speed
If traditional SAL is used, then device complexity is low, but clock-to-output delay increases at lower operating voltages
Solution Approach 1:
The patent implements periodic pre-charging of internal nodes during the clock cycle. The pre-charge circuit activates during specific phases to reset and pre-charge the differential pair nodes before the sensing phase, enabling faster response time and reduced clock-to-output delay. This periodic action ensures that the circuit is always ready to sense the next input transition quickly, even at low operating voltages.
Solution Approach 2:
The patent applies preliminary action by pre-charging the internal nodes and preparing the output latches before the actual sensing operation. The control circuit anticipates the need for fast response by pre-establishing the appropriate voltage levels and device states, thereby reducing the effective delay from clock to output when the actual sensing occurs.
3Reliability
If input sensing stage is always enabled, then sensing capability is maintained, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of the input sensing stage activation. The control circuit monitors the input common mode voltage and the output state of the decision-making circuit, enabling the sensing stage only when needed. During periods when the output state is already determined or when input voltage is outside the sensing range, the sensing stage is disabled to reduce power consumption while maintaining sensing capability when required.
Solution Approach 2:
The patent discards (disables) the input sensing stage when it is not needed for sensing, such as when the output state is already determined or when input voltage is outside the valid range. The control circuit manages the power state of the sensing stage, recovering power during idle periods while maintaining the ability to quickly re-enable sensing when needed, thus reducing overall power consumption.
Data Source
AI summary
Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.