Sense Amplifier Logic With Local Mask Storage for Fewer Row Cycles
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Solution Overview
Problem
Current memory devices require multiple row cycles to perform logical operations, leading to increased power consumption and processing time, especially when performing Boolean operations, due to the need for transferring masks, operands, and resultant data between rows.
Innovation Solution
Incorporating dedicated sensing circuitry with local storage for logical operation masking data, allowing for selective performance of logical operations within a memory device, reducing the number of row cycles and relying on static latches for active data storage rather than dynamic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple row cycles are used to perform logical operations, then logical operations can be completed, but power consumption increases and processing time increases
Solution Approach 1:
The patent segments the logical operation process into distinct phases (mask loading, operand loading, operation execution, result storage) that can be completed within a single row cycle. By organizing the circuitry and data flow to support this segmented approach, the system eliminates the need for multiple sequential row cycles, thereby reducing power consumption while maintaining reliable logical operation completion.
Solution Approach 2:
The patent implements preliminary action by pre-loading mask and operand data into dedicated buffer circuits before the logical operation is executed. This preparation phase allows the actual operation to be performed immediately when triggered, eliminating the need for multiple row cycles and reducing overall power consumption while ensuring reliable operation completion.
2Reliability
If multiple row cycles are used to perform logical operations, then logical operations can be completed, but processing time increases
Solution Approach 1:
The patent segments the logical operation into phases that can be executed within a single row cycle by dedicating specific circuits (mask buffer, operand buffer, operation circuit) to each phase. This segmentation enables parallel preparation and execution, completing the entire logical operation in one row cycle rather than multiple, thereby reducing processing time while maintaining reliable completion.
Solution Approach 2:
The patent introduces intermediary buffer circuits that temporarily store mask and operand data during the operation. These intermediaries enable rapid data transfer and operation execution within a single row cycle, eliminating the time delays associated with multiple row cycles while ensuring reliable logical operation completion.
3Reliability
If dynamic capacitance is used for data storage, then data can be stored, but power consumption increases
Solution Approach 1:
The patent employs static latches instead of dynamic capacitance for data storage in the mask buffer and operand buffer. Static latches maintain data without continuous power consumption, eliminating the energy waste associated with refreshing dynamic capacitance while ensuring reliable data storage throughout the logical operation process.
4Productivity
If dedicated sensing circuitry with local storage is incorporated, then logical operations can be performed with fewer row cycles, but device complexity increases
Solution Approach 1:
The patent merges the sensing circuitry with local storage elements (mask buffer, operand buffer) to create an integrated logical operation unit. This merging allows the sensing and storage functions to work together within a single row cycle, improving productivity by eliminating the need for multiple row cycles while managing device complexity through functional integration rather than separate components.
Solution Approach 2:
The patent designs the sensing circuitry with multi-functional capabilities, allowing it to serve both as a sensing element and as a local storage unit for mask and operand data. This universality enables the circuit to perform multiple functions (sensing, storing, and participating in logical operations) without proportionally increasing device complexity, thereby improving row cycle efficiency.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.