Sense Amplifier Architecture for Non-Volatile Memory Codeword Reading
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Solution Overview
Problem
Non-volatile memory technologies, such as PCM, face inefficiencies due to the need for differential architectures that require a doubled number of memory cells to store the same amount of information, resulting in reduced area density and storage capacity.
Innovation Solution
A sense amplifier architecture that allows information to be stored in coded manner using groups of non-volatile memory cells, where each group stores a codeword formed by the states of multiple cells, enabling efficient reading and decoding through comparison of cell currents and subset determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential architecture is used to ensure reliable reading, then reading reliability is improved, but the number of memory cells required doubles, reducing area density
Solution Approach 1:
The patent uses a copy of the stored value in a complementary memory cell to enable differential reading. Instead of requiring two cells for each bit of information, the system stores one value and its complement, allowing the sense amplifier to detect differences between the two cells without duplicating the information storage requirement.
Solution Approach 2:
The sense amplifier is designed to detect potential differences between complementary memory cells. By establishing a reference potential and comparing the actual cell potential against it, the system achieves reliable reading through differential measurement while maintaining efficient cell utilization.
2Quantity of substance
If more memory cells are used to store codewords, then storage capacity is improved, but area density deteriorates
Solution Approach 1:
The patent segments the memory array into multiple banks, with each bank capable of storing codewords. This segmentation allows parallel access to multiple codewords simultaneously, increasing effective storage capacity without proportionally increasing the area occupied by read circuitry, thereby improving area density.
Solution Approach 2:
The sense amplifier and comparison circuitry are designed to be universal, serving multiple memory cells and codeword groups. The same reading and comparison infrastructure can decode multiple codewords from different banks, eliminating the need for dedicated read circuits for each codeword and improving area efficiency.
3Productivity
If coded information storage is implemented, then storage efficiency is improved, but device complexity increases
Solution Approach 1:
The patent employs parameter changes in the form of coded representations of memory cell states. By encoding information using specific patterns of cell states (codewords with defined Hamming weights), the system achieves efficient storage and error detection without requiring complex decoding logic, as the code structure itself provides the necessary error correction capabilities.
4Measurement precision
If pairwise comparison of cell currents is performed, then decoding accuracy is improved, but reading time increases
Solution Approach 1:
The patent performs partial pairwise comparisons rather than exhaustive comparisons of all cell current combinations. By comparing cell currents in a structured sequence and using the results to progressively narrow down the decoded value, the system achieves accurate decoding without the time penalty of evaluating all possible codeword combinations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more compact and efficient memory occupation with improved storage density, requiring fewer memory cells while maintaining access time, thus enhancing the storage capacity of non-volatile memory devices.
Implementation Method 1
each sense amplifier reading branch (15) coupled to a respective memory cell (3) and configured to provide an output signal (sCOMP_A), which is indicative of a cell current (Icell) flowing through the same memory cell (3)
Implementation Method 2
a comparison stage (12), configured to perform a comparison between the cell currents (Icell) of memory cells (3) of a group
Data Source
AI summary
The present disclosure is directed to a sense amplifier architecture for a memory device having a plurality of memory cells. Groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high or logic low, of the memory cells of the group. The sense amplifier architecture has a plurality of sense amplifier reading branches, each sense amplifier reading branch coupled to a respective memory cell and configured to provide an output signal, which is indicative of a cell current flowing through the same memory cell; a comparison stage, to perform a comparison between the cell currents of memory cells of a group; and a logic stage, to determine, based on comparison results provided by the comparison stage, a read codeword corresponding to the group of memory cells. Information may be stored in different subsets of codewords, the sense amplifier architecture in this case having a subset definition circuit, to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.