Sense Amplifier Output Latch for Low-Area Memory Testing
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Solution Overview
Problem
Memory circuits designed for testability (DFT) incur significant area penalties due to the inclusion of idle components like sense amplifiers and output-Q-latches, as well as additional features such as write-in and shadow latches, 3-to-1 multiplexers, passive matrix isolation clamping circuits, and power-saving logic, which impact the overall circuit size and efficiency.
Innovation Solution
Replace the DFT D-flip-flop and write-in latch circuits with a read-out sense amplifier and data output latch, eliminating the need for write and shadow latches, and integrate a bypass circuit to utilize the sense amplifier for both read and write operations, thereby reducing area overhead and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional DFT components (write-in latch, shadow latch, 3-to-1 MUX, PM ISO clamping, power-saving logic) are incorporated into the memory circuit, then testability is improved, but area usage increases significantly
Solution Approach 1:
The sense amplifier is designed to perform multiple functions: it serves as both the read sense amplifier and the write-in latch circuit by utilizing the same physical components (first and second transistors) for both read and write operations, eliminating the need for separate dedicated circuits for each function
Solution Approach 2:
The patent merges the write-in latch circuit functionality into the read sense amplifier structure by using the first transistor for write operations and the second transistor for read operations, combining what were previously separate functional blocks into a unified circuit that reduces overall area usage
2Reliability
If additional DFT components are incorporated into the memory circuit, then testability is improved, but power consumption increases
Solution Approach 1:
The sense amplifier performs dual functions as both read sense amplifier and write-in latch, eliminating the need for separate dedicated circuits that would each consume power independently, thereby reducing total power consumption while maintaining full testability
Solution Approach 2:
By merging the write-in latch functionality into the read sense amplifier structure, the patent reduces the total number of active circuits that consume power, achieving lower overall power consumption while preserving all necessary test operations
3Reliability
If additional DFT components are incorporated into the memory circuit, then testability is improved, but device complexity increases
Solution Approach 1:
The sense amplifier is designed to perform multiple functions including read sensing, write-in latching, and test operations using the same physical components, thereby reducing device complexity by eliminating redundant dedicated circuits for each function
Data Source
AI summary
An input/output circuit comprises a bypass circuit, a first latch, a second latch, a first transistor, and a second transistor. The bypass circuit is configured to directly receive a data signal and indirectly receive a write enable signal. The first latch is coupled between a first data line and a second data line. The second latch is operatively coupled to the first latch and configured to generate a data output signal based on a voltage level presented on the second data line. The first transistor is coupled to the first latch and gated by a sense enable signal. The second transistor is coupled to the first latch and gated by a clock signal. The first transistor and the second transistor are alternately activated in each of a plurality of operation modes of the input/output circuit.