Semiconductor Storage Sense Amplifier Mode Switching
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Solution Overview
Problem
Current semiconductor storage devices, such as NAND flash memory, face challenges in optimizing current consumption during data write operations, with existing methods either increasing verify time or current consumption, depending on the lockout or no-lockout modes used.
Innovation Solution
The semiconductor storage device employs a sense amplifier circuit that switches between lockout and no-lockout modes based on the number of write loops or cell current values, optimizing current consumption by locking out bit lines at the start of the write sequence and transitioning to no-lockout mode as the write sequence progresses, thereby reducing overall current consumption and shortening the write sequence time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If lockout mode is used during verify operation, then current consumption is suppressed, but verify time increases
Solution Approach 1:
The patent applies dynamics by switching the sense amplifier between lockout and no-lockout modes based on the write loop counter value. Initially, the sense amplifier operates in lockout mode to suppress current consumption. When the write loop counter reaches a predetermined value, the mode switches to no-lockout to reduce verify time. This dynamic mode switching resolves the contradiction between current consumption and verify time by adapting the operation mode to the writing progress.
Solution Approach 2:
The patent implements periodic action by dividing the verify operation into distinct phases: an initial phase using lockout mode for current suppression, and a final phase using no-lockout mode for speed optimization. The transition between these phases is triggered by the write loop counter reaching a predetermined threshold, creating a structured, periodic pattern of operation that balances energy efficiency and speed.
2Loss of time
If no-lockout mode is used during verify operation, then verify time is reduced, but current consumption increases
Solution Approach 1:
The patent uses dynamics by conditionally switching between no-lockout and lockout modes based on the write loop counter. The no-lockout mode is activated only when the counter reaches a predetermined value, allowing the system to optimize verify time at the appropriate moment while suppressing current consumption during earlier stages. This dynamic control resolves the contradiction by applying each mode at the optimal time.
Solution Approach 2:
The patent structures the verify operation with periodic action by alternating between lockout mode (for current suppression) and no-lockout mode (for speed optimization) based on write loop counter thresholds. This creates a time-structured pattern where each mode serves its specific purpose at the appropriate phase of the writing process, resolving the contradiction between verify time and current consumption.
3Loss of energy
If lockout mode is used throughout the write sequence, then current consumption is suppressed, but write sequence time increases
Solution Approach 1:
The patent applies dynamics by transitioning the sense amplifier from lockout mode to no-lockout mode when the write loop counter reaches a predetermined value. This dynamic mode switching allows the system to suppress current consumption during initial write loops while reducing the total write sequence time in later stages, resolving the contradiction between energy efficiency and writing speed.
Solution Approach 2:
The patent implements periodic action by dividing the write sequence into phases: initial phases using lockout mode for current suppression, and final phases using no-lockout mode for speed optimization. The transition is triggered by the write loop counter reaching a predetermined threshold, creating a structured pattern that balances current consumption suppression with write sequence time reduction.
Data Source
AI summary
A semiconductor storage device according to an embodiment includes a memory cell array including a plurality of memory cells. A plurality of word lines are connected to the memory cells. A plurality of bit lines are connected to one end of current paths of the memory cells. A sense amplifier part is connected to the bit lines. A data write operation includes a first write loop and a second write loop. The first write loop includes a first program operation and a first verify operation. The second write loop includes a second program operation and a second verify operation. The sense amplifier part discharges a voltage of at least one of the bit lines in the first verify operation. The sense amplifier part keeps voltages of the bit lines in the second verify operation.