Sense-Amplifier Monotizer Circuit for Glitch-Free Latching
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Solution Overview
Problem
Conventional monotizers incur significant delay and degrade performance due to their implementation, which affects the transition of computation from CMOS logic to dynamic logic, leading to glitch-free operation issues.
Innovation Solution
A sense-amplifier monotizer is introduced, comprising an amplifier circuit and a keeper circuit that samples data and maintains the logic state during specific clock phases, reducing delay and enhancing system performance by using shared NMOS transistors and gates like NAND, NOR, and inverters to manage clock signals and data transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional monotizer implementation is used, then the logic state can be latched in a race-free manner, but significant delay is incurred and performance degrades
Solution Approach 1:
The monotizer circuit is segmented into distinct functional blocks: a latch circuit for race-free sampling, a sense amplifier circuit for rapid signal amplification, and a keeper circuit for state maintenance. This segmentation allows each component to be optimized independently, with the sense amplifier providing fast operation to reduce overall delay while the latch ensures reliability.
Solution Approach 2:
A sense amplifier is introduced as an intermediary component between the latch circuit and the output. The sense amplifier rapidly amplifies the latched signal, bridging the gap between the relatively slow latch operation and the need for fast output transitions. This intermediary enables the system to maintain race-free latching while significantly reducing the overall computational delay.
2Reliability
If the monotizer operates with conventional circuitry, then it can ensure robust glitch-free operation, but the transition speed from CMOS logic to dynamic logic is reduced
Solution Approach 1:
The circuit employs dynamic operation modes where transistors are switched between different states (on/off, linear/saturation) based on the clock phase. During the evaluation phase, the sense amplifier operates in a high-speed dynamic mode that enables rapid signal transitions. The keeper circuit dynamically maintains the state only when needed, allowing fast transitions while ensuring glitch-free operation through controlled timing.
Solution Approach 2:
The circuit parameters such as transistor width, length, and gate voltage are dynamically adjusted based on the operating phase. The sense amplifier uses variable gain control to optimize both speed and stability. By changing parameters like the strength of the keeper circuit and the bias conditions of the latch, the circuit achieves fast transitions during evaluation while maintaining robust glitch-free operation during stable states.
Data Source
AI summary
A sense-amplifier monotizer includes an amplifier circuit and a keeper circuit. The amplifier circuit outputs a predetermined logic state while a clock signal is in a first phase, and samples a data signal and outputs at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase. A subsequent change of the data signal does not affect an output of the amplifier circuit once the data signal is sampled while the clock signal is in the second phase. The keeper circuit keeps a logic state of the sampled data signal once the data signal is sampled while the clock signal is in the second phase. The amplifier circuit may receive multiple data signals, and output a data signal selected by the select signal and/or a complementary value while the clock signal is in the second phase.