Sense Amplifier Circuit for NAND Flash Memory Write Speed
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Solution Overview
Problem
Current NAND flash memory devices face challenges in achieving high-speed write operations due to separate time periods for charge transfer to bit lines and verify result transfer, which prolongs operation time and increases power consumption.
Innovation Solution
The non-volatile semiconductor memory device utilizes the same voltage level for both bit line transfer and detection circuit during write operations, allowing simultaneous write operation and verify result transfer, thereby reducing operation time and power consumption by reusing already set voltages and discharging accumulated charge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate time periods are used for charge transfer to bit lines and verify result transfer, then data integrity is ensured, but operation time is prolonged and power consumption increases
Solution Approach 1:
The patent merges the charge transfer operation and verify result transfer operation into a single simultaneous operation. The sense amplifier circuit performs both functions at the same time by transferring charge to the bit line while simultaneously transferring the verify result to the external device, eliminating the need for separate time periods and reducing total operation time while maintaining data integrity through the dual-function design
2Reliability
If separate time periods are used for charge transfer to bit lines and verify result transfer, then operational reliability is maintained, but power consumption increases
Solution Approach 1:
The patent combines two separate operations (charge transfer and verify result transfer) into one simultaneous operation, thereby reducing the total duration for which power must be supplied. By performing both transfers at the same time through the sense amplifier circuit, the system reduces overall power consumption while maintaining operational reliability through the integrated design
3Productivity
If write operation speed is increased by simultaneous operations, then productivity improves, but risk of erroneous writing increases
Solution Approach 1:
The patent uses the sense amplifier circuit as an intermediary device that coordinates and manages the simultaneous charge transfer and verify result transfer operations. This intermediary circuit ensures proper timing and sequencing, allowing high-speed simultaneous operations while preventing erroneous writing through controlled signal management and verification before data is written to the memory cell
Data Source
AI summary
According to one embodiment, a non-volatile semiconductor memory device which is provided with a memory cell array, bit lines, word lines, and a sense amplifier circuit is presented. The memory cell array includes memory cells. The bit lines are electrically connected to the memory cells. The word lines are electrically connected to gates of the non-volatile memory cells. The sense amplifier circuit includes sense amplifiers which are electrically connected to the bit lines. Each of the sense amplifiers includes a latch circuit which is capable of holding data, and a detection circuit. The sense amplifiers are configured to apply any one of a first voltage and a second voltage higher than the first voltage to the bit lines respectively. The sense amplifiers apply any one of the first voltage and the second voltage s a third voltage to the bit lines, and apply the third voltage to the detection circuit.