Bitline Sense Amplifier Noise Isolation in DRAM
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Solution Overview
Problem
Existing dynamic random access memory (DRAM) devices face challenges due to noise during sensing and amplification operations of bitline sense amplifiers, which reduces the sensing margin and degrades overall performance.
Innovation Solution
A memory device architecture that includes a first semiconductor layer with a memory cell array and bitlines, and a second semiconductor layer with a peripheral circuit and a bitline sense amplifier. The bitline sense amplifier features a transistor pair shared by control lines, allowing for stable control voltage supply without interference from surrounding amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional bitline sense amplifier architecture is used, then device complexity is reduced, but noise increases and sensing margin deteriorates
Solution Approach 1:
The bitline sense amplifier is divided into multiple independent amplifier units, each handling specific bitlines. This segmentation isolates noise sources within each unit while maintaining overall system functionality, thereby improving sensing margin without proportionally increasing overall device complexity.
Solution Approach 2:
The patent introduces a new architectural dimension by implementing a hierarchical amplifier structure with master and slave amplifiers operating at different levels. This dimensional change allows for better noise management and sensing margin improvement while controlling complexity through structured organization.
2Productivity
If bitline sense amplifier operates at high speed, then productivity is improved, but noise increases and sensing margin is reduced
Solution Approach 1:
The amplifier operates in periodic cycles with distinct phases for sensing and amplification. During sensing phase, high-speed operation is maintained for productivity, while during amplification phase, the isolated amplifier units maintain stable sensing margins. This periodic operation resolves the contradiction between speed and reliability.
Solution Approach 2:
The master amplifier performs preliminary amplification of bitline signals before they are processed by slave amplifiers. This preliminary action at high speed prepares the signals in advance, allowing subsequent stages to operate with improved sensing margins without sacrificing overall operating speed.
3Area of stationary object
If multiple bitline sense amplifiers are placed close together, then area is reduced, but noise from surrounding amplifiers increases
Solution Approach 1:
Isolation structures and shielding elements are introduced as intermediaries between adjacent amplifier units. These intermediaries physically separate the amplifiers, reducing crosstalk noise while allowing the amplifiers to remain in close proximity, thereby maintaining small area occupation.
Solution Approach 2:
Each amplifier unit is designed with localized noise isolation characteristics, where specific regions of each amplifier have enhanced shielding properties. This local quality approach allows compact arrangement of amplifiers while maintaining low crosstalk through position-dependent noise management.
Data Source
AI summary
A memory device includes a first semiconductor layer and a second semiconductor layer disposed with respect to the first semiconductor layer in a third direction. The first semiconductor layer includes a memory cell array, a bitline and a complementary bitline coupled with the memory cell array, a first vertical wire coupled with the bitline, and a second vertical wire coupled with the complementary bitline. The second semiconductor layer includes a peripheral circuit, a bitline sense amplifier, first and second control lines coupled with the bitline sense amplifier, a third vertical wire coupled with the bitline sense amplifier, and a fourth vertical wire coupled with the bitline sense amplifier. The bitline sense amplifier includes at least one first transistor pair that is shared by at least one of the first and second control lines.