Bit Line Sense Amplifier Offset Cancellation Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional bit line sense amplifier circuits fail to accurately sense and amplify potential differences between bit lines due to offset voltages caused by transistor mismatches, leading to inaccurate data polarity determination and amplification.
Innovation Solution
A bit line sense amplifier circuit with an offset canceling period and amplification period, utilizing a first down-converter to generate a second pull-up voltage, a capacitor for charging, and specific supply configurations to reduce offset and enhance voltage difference amplification, including isolation and offset canceling switches, and a power equalizer to manage voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional bit line sense amplifier circuits are used, then the circuit structure is simple, but offset voltages cause inaccurate sensing and amplification of potential differences
Solution Approach 1:
The patent applies preliminary action by performing an offset canceling operation before the main amplification operation. During the offset canceling period, the bit line sense amplifier circuit proactively compensates for offset voltages by adjusting the pull-up voltage to match the pull-down voltage, ensuring that the amplifier is calibrated before actual data sensing begins. This preliminary calibration eliminates measurement errors that would otherwise compromise sensing accuracy.
Solution Approach 2:
The patent implements dynamics by making the pull-up voltage dynamic rather than fixed. A voltage converter dynamically adjusts the pull-up voltage level based on operating conditions, allowing the circuit to adapt to varying offset conditions. This dynamic voltage adjustment enables the amplifier to maintain high sensing accuracy across different operating scenarios while managing circuit complexity through controlled adaptability.
2Reliability
If transistor mismatches are present, then manufacturing is easier, but offset voltages increase leading to inaccurate data polarity determination
Solution Approach 1:
The patent applies feedback by using the output of the bit line sense amplifier circuit to adjust the pull-up voltage through a voltage converter. The circuit continuously monitors the potential difference between bit lines and feeds this information back to dynamically adjust the pull-up voltage level, compensating for transistor mismatches. This feedback mechanism ensures that even with manufacturing variations, the amplifier maintains accurate data polarity determination by adaptively correcting for offset voltages.
Solution Approach 2:
The patent implements parameter changes by varying the pull-up voltage parameter to compensate for transistor mismatches. Instead of relying on precise transistor matching, the circuit changes the operating voltage parameter dynamically to maintain optimal performance. This approach shifts the burden from manufacturing precision to operational flexibility, allowing the circuit to achieve high reliability despite variations in transistor characteristics.
3Measurement precision
If offset canceling operations are implemented, then sensing accuracy improves, but the operation time increases due to additional periods
Solution Approach 1:
The patent applies periodic action by structuring the operation into distinct periodic phases: an offset canceling period followed by an amplification period. During the offset canceling period, the circuit focuses solely on calibration; during the amplification period, it performs data sensing. This periodic structuring ensures that the offset canceling operation does not continuously interfere with amplification, allowing both functions to be performed with optimal timing and resource allocation, thereby minimizing overall time loss while maintaining high sensing accuracy.
Data Source
AI summary
A memory may include: a bit line sense amplifier circuit configured to operate based on voltages supplied to a pull-up voltage terminal and a pull-down voltage terminal, provide an offset between a first bit line and a second bit line during an offset canceling period, and amplify a voltage difference between the first bit line and the second bit line during an amplification period; a first down-converter configured to generate a second pull-up voltage by down-converting a first pull-up voltage and supply the generated second pull-up voltage to a first node; a capacitor electrically connected to the first node; a charging component configured to charge the capacitor with the first pull-up voltage before the offset canceling period; and a first pull-up supply configured to supply a voltage of the first node to the pull-up voltage terminal during the offset canceling period.