Sense Amplifier Offset Compensation for Faster SRAM Read Access
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Solution Overview
Problem
The existing sense amplifiers in memory cells, such as SRAM, experience longer wait times due to amplifier offsets, which delay the read operation and increase overall access time.
Innovation Solution
A compensation circuit is introduced to reduce or eliminate the offset of the sense amplifier, allowing it to sense a smaller bit line split, thereby increasing read access speed by over 20% by applying a control sequence that pre-charges and equalizes bit lines to compensate for transistor mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sense amplifier is turned on when the bit line split is greater than an offset plus margins, then the read operation is reliable, but the wait time is prolonged
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit lines to equal voltage levels before the read operation begins. This preliminary equalization eliminates the need to wait for the bit line split to exceed the amplifier offset, as the amplifier can immediately detect the voltage difference when the memory cell is accessed. The pre-charge phase prepares the bit lines in advance, removing the delay caused by offset compensation requirements.
2Productivity
If the amplifier offset is not compensated, then the device complexity is low, but the read access speed is reduced
Solution Approach 1:
The patent changes the voltage parameter of the bit lines by applying a pre-charge signal that equalizes their voltage levels before the read operation. This parameter change (voltage equalization) compensates for the amplifier offset without requiring complex circuit modifications. The pre-charge signal adjusts the bit line voltages to a specific state that eliminates offset effects, achieving fast read access with minimal additional circuitry.
3Measurement precision
If the sense amplifier waits for sufficient bit line split development, then the offset effect is minimized, but the access time increases
Solution Approach 1:
The patent performs preliminary action by pre-charging the bit lines to equal voltage levels before the read operation. This preliminary equalization ensures that when the memory cell is accessed, the bit line split develops immediately without delay, allowing the sense amplifier to detect the voltage difference right away. The pre-charge phase prepares the bit lines in advance, eliminating the wait time required for sufficient split development while maintaining detection accuracy.
Data Source
AI summary
A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage.