Sense Amplifier Offset Compensation Using Test Code Latches

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Solution Overview

Problem

Sense amplifier voltage offsets due to process variations in semiconductor memory devices lead to errors during data cell and reference cell comparisons, reducing sensing margin and causing errors in logic value determination.

Innovation Solution

A circuit and method that utilize a trimming circuit and test mode control circuit to adjust current provided to bit lines, using test codes to determine an offset compensation code that compensates for voltage offsets in the sense amplifier, thereby reducing errors during sensing operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sense amplifier is used to compare data cell and reference cell voltages, then data sensing function is achieved, but voltage offset due to process variations causes errors in logic value determination

Engineering Contradiction:
Improveaccuracy of logic value determinationVSAvoidsensing margin
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by performing offset calibration before normal sensing operations. During a calibration mode, the sense amplifier offset is measured and stored, then compensated during subsequent read operations. This preliminary calibration action eliminates the voltage offset error that would otherwise reduce sensing margin and cause logic value determination errors.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the operating parameters of the sense amplifier by adjusting its offset voltage through calibration. By measuring the actual offset voltage and applying a compensating adjustment, the sense amplifier's voltage comparison threshold is shifted to account for process variations, thereby maintaining accurate logic value determination despite manufacturing tolerances.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If process variations occur during manufacturing, then device fabrication is simplified, but voltage offset in sense amplifier increases causing sensing errors

Engineering Contradiction:
Improvefabrication process toleranceVSAvoidsensing accuracy
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements feedback by measuring the actual voltage offset in the sense amplifier and using this information to compensate for the offset during normal operation. The calibration process creates a feedback loop where the sensed offset is fed back into the system to adjust future measurements, thereby maintaining sensing accuracy despite process variations that occur during manufacturing.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The sense amplifier system performs self-calibration by automatically measuring its own offset voltage and applying compensation without requiring external intervention. The calibration circuitry is integrated into the sense amplifier itself, allowing the device to self-correct for process variations and maintain accurate sensing performance.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP3025350B1Sense amplifier offset voltage reduction using test code stored in latches
Publication Date: 2019.11.20 QUALCOMM INC
  • EP3025350B1 patent drawingFigure 1
  • EP3025350B1 patent drawingFigure 2
  • EP3025350B1 patent drawingFigure 3

AI summary

A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.