Bit-Line Sense Amplifier Over-Drive Voltage for DRAM Retention
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Solution Overview
Problem
Dynamic random access memory (DRAM) semiconductor memory cells face a short data retention time due to increased leakage components, necessitating a technology to improve data maintenance reliability.
Innovation Solution
A semiconductor memory apparatus with a bit-line sense amplifier and power supply unit that uses pull up and pull down drive voltages in active and precharge modes, along with an over drive voltage to extend data retention time by activating the pull up over drive power drive signal for a predetermined time and supplying an over drive voltage until the memory cell is deactivated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If leakage component is increased in DRAM memory cells, then data retention time becomes short, but using conventional drive voltages cannot maintain data integrity
Solution Approach 1:
The patent applies parameter changes by switching from conventional drive voltages to over-drive voltages (higher than standard VDD) during the precharge phase. This voltage parameter change compensates for leakage effects by providing stronger electric fields that maintain charge integrity in memory cells even when leakage components increase, thereby extending reliable data retention time.
Solution Approach 2:
The patent implements preliminary action by applying over-drive voltages to the bit-line sense amplifier during the precharge mode before actual data access operations. This preliminary high-voltage application pre-charges the bit-lines and sense amplifier circuits to higher voltage levels, creating a stronger initial state that compensates for upcoming leakage effects and extends the window for reliable data retention.
2Reliability
If over drive voltage is supplied to extend data retention time, then data integrity is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by using over-drive voltages only during specific precharge phases rather than continuously. The bit-line sense amplifier operates with conventional drive voltages during normal active modes but switches to over-drive voltages during precharge modes. This periodic application of high voltage extends data retention time while limiting power consumption increases to only the necessary precharge intervals.
Solution Approach 2:
The patent implements partial action by applying over-drive voltages selectively to the bit-line sense amplifier rather than to the entire memory system. Only the sense amplifier and associated bit-line circuits receive the excessive voltage during precharge, while the rest of the memory array operates with standard voltages. This partial application achieves data integrity improvement with minimized power consumption impact.
Data Source
AI summary
Disclosed is a semiconductor memory apparatus which improves the time to transmit write data to a memory cell and improves data retention time of the memory cell. To this end, the semiconductor memory apparatus includes a bit-line sense amplifier that senses and amplifies data of bit-line pairs by driving power supplied through a pull up power line and a pull down power line and transmits the amplified data to a memory cell. A bit-line sense amplification power supply unit supplies pull up driving voltage and pull down driving voltage to the pull up and pull down power lines in an active mode and supplies an over driving voltage and the pull down driving voltage having a higher voltage level than the pull up driving voltage to the pull up and pull down power lines until the memory cell is deactivated in a precharge mode.