Bit Line Sense Amplifier Driver With Over Driving Signal
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in efficiently driving the bit line sense amplifier due to high capacitance and large resistance in bit lines, leading to significant time requirements for conveying data during write operations.
Innovation Solution
A driving signal generating circuit is introduced that includes an over driver and a normal driver, with a delay circuit and inverters to generate over and normal driving signals, allowing the bit line sense amplifier to be driven by a higher power supply voltage for a predetermined interval, improving driving power and reducing write recovery time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bit line sense amplifier is driven by conventional voltage levels, then the circuit operation is stable, but the writing speed is slow due to high capacitance and large resistance in bit lines
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit lines to a higher voltage level (e.g., VDD or VDDH) before the write operation begins. This pre-charging is controlled by a write prepare signal that activates earlier than the main write signal, ensuring the bit lines are ready to rapidly accept data during the write operation, thereby improving writing speed without excessive power consumption during normal operation
Solution Approach 2:
The patent implements dynamics by using dynamic voltage control of the bit lines through multiple voltage levels (VSS, VDD, VDDH) and time-varying control signals. The bit line voltage transitions between different levels based on the operation phase (read vs. write), allowing the system to optimize performance for each operation type while managing power consumption effectively
2Productivity
If the pull-up power supply voltage is increased to improve driving power, then the writing operation becomes faster, but the power consumption increases
Solution Approach 1:
The patent applies periodic action by using time-divided voltage control where the high voltage level (VDDH) is applied only during specific write operation intervals rather than continuously. The write prepare signal and write signal are activated in specific time sequences, ensuring high power is consumed only when necessary for rapid data writing, while normal operation uses lower voltage levels to minimize power consumption
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the pull-up power supply voltage level based on the operation mode. During write operations, the voltage is temporarily increased to VDDH to improve writing speed, while during read operations or idle states, the voltage remains at the normal VDD level, thus achieving speed improvement without proportional increase in overall power consumption
Data Source
AI summary
A semiconductor memory device includes an over driver for driving a pull-up power line of a bit line sense amplifier by an over driving signal, a normal driver for driving the pull-up power line of the bit line sense amplifier by a normal driving signal, and a driving signal generating circuit, in response to a write signal, for generating a driving signal to drive the over driver for a predetermined interval and thereafter to drive the normal driver.