Sense Amplifier Pre-Charging for Memory Read Speed

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Solution Overview

Problem

As integrated circuits evolve to smaller device geometries, sense amplifiers in memory systems face challenges with low cell currents, leading to slower and less accurate read operations due to reduced sensitivity.

Innovation Solution

A system and method for a high-performance sense amplifier using an operational amplifier, switch, comparator, and current generator to pre-charge bit lines to a reference voltage, employing an anti-charge-injection switch to control the pre-charging process and detect current changes, thereby improving sensitivity and speed of read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device geometry is reduced to increase circuit density, then more devices can be fabricated on each wafer, but sense amplifier sensitivity deteriorates due to lower cell current

Engineering Contradiction:
Improvecircuit densityVSAvoidsense amplifier sensitivity
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The operational amplifier pre-charges the bit line to a reference voltage before the actual sensing operation. This preliminary action ensures that the bit line starts at a known voltage level, maximizing the voltage swing and sensitivity during the subsequent sensing phase, thereby compensating for the reduced cell current in scaled devices

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the operating parameters of the sense amplifier by using an operational amplifier configured to maintain the bit line voltage close to the reference voltage throughout the sensing process. This parameter control approach ensures optimal sensitivity despite the reduced cell current from smaller memory cells

Inventive Principle:
Principle #35Parameter changes

2Productivity

If device geometry is reduced to increase circuit density, then more devices can be fabricated on each wafer, but read operation speed deteriorates due to lower cell current

Engineering Contradiction:
Improvecircuit densityVSAvoidread operation speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The operational amplifier performs preliminary pre-charging of the bit line to the reference voltage, ensuring that when the sensing operation begins, the bit line is already at the optimal voltage level. This eliminates delays associated with gradual charging and enables faster read operations despite lower cell currents

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The operational amplifier uses feedback to continuously monitor and adjust the bit line voltage, keeping it close to the reference voltage during the sensing process. This feedback mechanism ensures rapid response and maintains high read operation speed by preventing voltage deviations that would slow down the sensing process

Inventive Principle:
Principle #23Feedback

3Productivity

If device geometry is reduced to increase circuit density, then more devices can be fabricated on each wafer, but read operation accuracy deteriorates due to lower cell current

Engineering Contradiction:
Improvecircuit densityVSAvoidread operation accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

By pre-charging the bit line to the reference voltage before sensing, the operational amplifier ensures that the starting voltage level is precise and known. This preliminary action establishes a stable baseline that improves the accuracy of the subsequent sensing operation, compensating for the reduced signal strength from smaller memory cells

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The operational amplifier employs feedback to maintain the bit line voltage close to the reference voltage throughout the sensing process. This continuous voltage regulation ensures that the sensing operation occurs at the optimal voltage point, maximizing accuracy even with lower cell currents from scaled devices

Inventive Principle:
Principle #23Feedback

4Measurement precision

If operational amplifier is used to pre-charge bit line to reference voltage, then sensitivity and speed are improved, but device complexity increases

Engineering Contradiction:
Improvesense amplifier sensitivityVSAvoidsense amplifier complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The operational amplifier performs multiple functions: it acts as a pre-charger to set the bit line voltage to the reference level, and simultaneously serves as a buffer to maintain this voltage during sensing. By combining these functions in a single device, the patent improves sensitivity without proportionally increasing complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the pre-charge function and the buffer function into a single operational amplifier circuit. This consolidation achieves the desired sensitivity improvement while minimizing the increase in device complexity by using a multi-functional component rather than separate dedicated circuits

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7787321B2High performance sense amplifier and method thereof for memory system
Publication Date: 2010.08.31 SEMICON MFG INT (SHANGHAI) CORP
  • US7787321B2 patent drawing
  • US7787321B2 patent drawing
  • US7787321B2 patent drawing

AI summary

A system and method for sensing a current. The system includes an operational amplifier including a first input terminal, a second input terminal, and a first output terminal. The first input terminal is biased to a predetermined voltage, and the second input terminal and the first output terminal are directly connected. Additionally, the system includes a switch coupled to the first output terminal and a first node. The switch is controlled by at least a first control signal. Moreover, the system includes a comparator including a third input terminal, a fourth input terminal, and at least a second output terminal. The comparator is configured to receive a first input signal at the third input terminal and a second input signal at the fourth input terminal. The first input signal and the second input signal are associated with the first node and the predetermined voltage.