Sense Amplifier Pulse Control for Semiconductor Storage Signal Detection
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Solution Overview
Problem
In semiconductor storage devices, the sense amplifier struggles to accurately detect signal levels from memory cells due to potential errors in magnitude determination and delayed operations caused by varying capacitance values of capacitive elements, which affects the speed and reliability of signal detection.
Innovation Solution
The semiconductor storage device employs a configuration with a sense amplifier that supplies positive and negative potential pulses to capacitive elements, ensuring sufficient signal levels while accelerating the sense amplifier operation by adjusting the capacitance values of capacitive elements and controlling pulse amplitudes based on bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitance value of capacitive elements in the sense amplifier is increased to ensure sufficient signal levels, then the reliability of signal detection is improved, but the operation time of the sense amplifier increases causing delayed detection
Solution Approach 1:
The patent applies periodic action by using pulse generation circuits to supply periodic positive and negative pulses to the capacitive elements. These pulses are supplied at specific timing during the sense amplifier operation, creating a rhythmic charging pattern that accelerates the charging process while maintaining sufficient signal levels for reliable detection
Solution Approach 2:
The patent changes the parameters of the capacitive elements by dynamically adjusting their capacitance values and the amplitudes of the supplied pulses. The pulse generation circuits modify the electrical parameters (voltage amplitude, timing) based on operational requirements, allowing the system to achieve both fast operation and reliable detection by optimizing these parameters rather than using fixed large capacitance values
2Measurement precision
If the capacitance values of capacitive elements are varied to optimize signal levels, then the accuracy of magnitude determination is improved, but the device complexity increases due to multiple pulse generation circuits
Solution Approach 1:
The patent segments the pulse generation function into separate positive pulse generation circuit and negative pulse generation circuit. Each circuit independently controls one type of pulse, allowing for simplified individual circuit designs while achieving the complex overall effect of differential capacitive charging. This segmentation makes the system more manageable and easier to implement than a single complex control circuit
Solution Approach 2:
The patent applies preliminary action by pre-charging the capacitive elements with positive and negative pulses before the actual comparison operation. This preparatory charging action ensures that when the memory cell signal is applied, the capacitive elements are already at optimal voltage levels, enabling accurate magnitude determination without requiring complex real-time adjustment circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy and speed of signal detection, reducing bit errors and improving overall performance by securing signal levels and shortening operation times.
Implementation Method 1
a first capacitive element having one end connected to the first data line and the other end connected to a node; a second capacitive element having one end connected to the second data line and the other end connected to the node
Data Source
AI summary
According to the embodiment, in a first period, the semiconductor storage device maintains the switch in an ON state. In a second period, the semiconductor storage device performs a first operation, a second operation and a third operation while maintaining the switch in an OFF state. The second period is a period after the first period. The first operation is an operation to supply the first pulse having the first polarity from the first pulse generation circuit to the other end of the first capacitive element. The second operation is an operation to supply the second pulse having the second polarity from the second pulse generation circuit to the other end of the second capacitive element. The third operation is an operation to connect the first bit line to the first data line.


