Sense Amplifier Pulsed Control for Glitch-Free Speed
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Solution Overview
Problem
Conventional sense amplifiers face timing issues and glitches due to the simultaneous switching on of differential pair transistors when the sense enable signal is asserted too quickly after the word line voltage, leading to reduced memory operating speeds.
Innovation Solution
The introduction of a pair of first pull-up transistors that charge the output terminals during an initial portion of the sense enable signal assertion and switch off in response to a delayed sense enable signal, allowing for reduced timing delay between the word line and sense enable signal assertions, and a pair of always-on second pull-up transistors to facilitate quick sense enable signal assertion without glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the sense enable signal is asserted quickly after the word line voltage to increase operating speed, then the memory operating speed is improved, but glitches occur in the differential output voltage due to simultaneous discharge of both drains
Solution Approach 1:
The pull-up function is segmented into two distinct transistor groups: first pull-up transistors (P3, P4) that are controlled by the delayed sense enable signal to prevent glitches during the initial phase, and second pull-up transistors (P5, P6) that remain always-on to maintain output stability. This segmentation allows each transistor group to specialize in different phases of operation, resolving the contradiction between speed and reliability.
Solution Approach 2:
The first pull-up transistors are activated in advance (always-on or with delayed enable) to pre-charge the output terminals and prepare the circuit before the differential pair transistors switch on. This preliminary action ensures that when the sense enable signal is asserted quickly, the output terminals already have sufficient charge to prevent glitches, thereby enabling high-speed operation without compromising output stability.
2Reliability
If keeper transistors are sized to have sufficient strength to prevent glitches, then output voltage stability is improved, but a relatively long delay is required between word line and sense enable signal assertions
Solution Approach 1:
The pull-up function is segmented into two distinct transistor groups: first pull-up transistors (P3, P4) that are controlled by the delayed sense enable signal to prevent glitches during the initial phase, and second pull-up transistors (P5, P6) that remain always-on to maintain output stability. This segmentation allows each transistor group to specialize in different phases of operation, resolving the contradiction between speed and reliability.
Solution Approach 2:
The first pull-up transistors operate periodically: they are active during the initial portion of the sense enable signal assertion to prevent glitches, then switch off when the delayed sense enable signal is asserted. This periodic operation allows strong pull-up strength when needed without requiring continuous strong opposition, thereby reducing the required timing delay compared to always-on keeper transistors.
3Reliability
If the first pull-up transistors remain always-on to prevent glitches, then output voltage stability is improved, but the strength required reduces the speed at which differential output voltage can be developed
Solution Approach 1:
The pull-up function is segmented into two distinct transistor groups: first pull-up transistors (P3, P4) that are controlled by the delayed sense enable signal to prevent glitches during the initial phase, and second pull-up transistors (P5, P6) that remain always-on to maintain output stability. This segmentation allows each transistor group to specialize in different phases of operation, resolving the contradiction between speed and reliability.
Solution Approach 2:
The first pull-up transistors operate periodically: they are active during the initial portion of the sense enable signal assertion to prevent glitches, then switch off when the delayed sense enable signal is asserted. This periodic operation allows strong pull-up strength when needed without requiring continuous strong opposition, thereby reducing the required timing delay compared to always-on keeper transistors.
Data Source
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AI summary
A sense amplifier is provided with a pair of first pull-up transistors that are configured to charge a corresponding pair of output terminals while a delayed sense enable signal is not asserted and to stop charging the corresponding pair of output terminals while the delayed sense enable signal is asserted.