Sense Amplifier Readout Conditioning for Mixed-Capacity Memory Circuits

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Solution Overview

Problem

Semiconductor storage devices with memory circuits of different storage capacities face issues in signal waveform differences leading to incorrect bit value readings or delayed operations when using a common reference voltage, affecting reading speed and accuracy.

Innovation Solution

Implementing a readout conditioning circuit that adjusts the operation timing and reference voltage of the sense amplifier based on the memory circuit type, using delay circuits and power circuits to optimize voltage differences and reduce readout failures while maintaining speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the reference voltage is set based on the memory circuit having a larger storage capacity, then the sense amplifier can correctly read bit values from large capacity circuits, but it incorrectly reads bit values from small capacity circuits

Engineering Contradiction:

Improvebit value reading accuracyVSAvoidreading correctness

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent implements a readout conditioning circuit that dynamically adjusts the reference voltage based on which memory circuit (first or second) is being read. The control circuit selects between a first reference voltage for the first memory circuit and a second reference voltage for the second memory circuit, making the reference voltage adaptive rather than fixed. This resolves the contradiction by allowing the system to optimize reading accuracy for each memory circuit type without compromise.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the reference voltage parameter depending on the memory circuit being accessed. By providing different reference voltage levels matched to the characteristics of each memory circuit type, the system achieves accurate bit value determination for both large and small capacity circuits. This parameter adaptation directly addresses the measurement precision issue.

Inventive Principle:

Principle #35Parameter changes

2Speed

If the reference voltage is set based on the memory circuit having a smaller storage capacity, then the sense amplifier reads bit values quickly, but the reading speed becomes slower due to delayed operation

Engineering Contradiction:

Improvereading speedVSAvoidoperation delay

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The readout conditioning circuit dynamically adjusts operation timing based on the selected memory circuit. The control circuit configures the sense amplifier to operate at timing optimized for the specific memory circuit type being accessed, preventing operation delays while maintaining fast reading speed. This dynamic timing adjustment resolves the speed-time contradiction.

Inventive Principle:

Principle #15Dynamics

3Device complexity

If a common reference voltage is used for both memory circuits, then the device structure is simplified, but signal waveform differences cause incorrect readings

Engineering Contradiction:

Improvereference voltage configurationVSAvoidbit value determination accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent segments the reference voltage configuration into separate reference voltages for different memory circuits. Instead of using a single common reference voltage, the system provides a first reference voltage for the first memory circuit and a second reference voltage for the second memory circuit. This segmentation allows each memory circuit to operate with its optimal reference voltage, resolving the measurement precision issue while the control logic manages the complexity.

Inventive Principle:

Principle #1Segmentation

4Ease of operation

If the sense amplifier operates with fixed timing, then the operation is simple, but it cannot accommodate different signal waveforms from memory circuits of different capacities

Engineering Contradiction:

Improvesense amplifier operationVSAvoidcompatibility with different memory circuits

Core Design Contradiction:

Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic operation timing for the sense amplifier that adapts to the selected memory circuit type. The control circuit configures the sense amplifier to operate at timing optimized for the specific memory circuit being accessed, enabling the system to accommodate different signal waveforms from memory circuits of different capacities while maintaining ease of operation through automated control.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250391449A1Semiconductor storage device including sense amplifier that senses data from multiple memory circuits

Publication Date: 2025.12.25 KK TOSHIBA

AI summary

A semiconductor storage device according to an embodiment comprises: a first memory circuit; a second memory circuit having a storage capacity smaller than that of the first memory circuit; a readout line commonly connected to the first memory circuit and the second memory circuit; a sense amplifier configured to compare a voltage of a first bit signal or a second bit signal with a reference voltage, where the first bit signal being inputted from the first memory circuit through the readout line and the second bit signal being inputted from the second memory circuit through the readout line; and a readout conditioning circuit configured to change at least one of an operation timing of the sense amplifier and the reference voltage corresponding to the first bit signal and the second bit signal.