Sense Amplifier Logic Circuitry for Fewer Memory Row Cycles
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Solution Overview
Problem
Current memory devices require multiple row cycles for logical operations, leading to increased power consumption and processing time, especially when performing Boolean operations, due to the need for data transfer between rows and reliance on dynamic capacitance for operand storage.
Innovation Solution
Incorporating dedicated sensing circuitry with static latches and selection logic circuitry within the memory array to perform logical operations locally, reducing the need for row operations and minimizing power consumption by storing masking data locally and shifting data synchronously between sensing components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between rows for logical operations, then logical operations can be performed, but processing time increases
Solution Approach 1:
The patent combines the memory array and sensing circuitry into an integrated processing-in-memory architecture. The sensing circuitry is directly coupled to memory rows, allowing logical operations to be performed within the memory device itself rather than transferring data to external processors. This merging of storage and processing functions eliminates data transfer time and enables logical operations to be completed in fewer row cycles.
Solution Approach 2:
The sensing circuitry acts as an intermediary component between the memory array and external processors. It retrieves data from memory rows, performs logical operations locally, and returns results without requiring full data transfer to external processing units. This intermediary function reduces processing time by keeping operations within the memory device.
2Adaptability or versatility
If multiple row cycles are used for logical operations, then complex operations can be performed, but power consumption increases
Solution Approach 1:
The integration of sensing circuitry with memory rows enables multiple logical operations to be performed within a single row cycle. By combining retrieval and processing functions in the same location, the system can execute complex logical operations without the additional power consumption associated with multiple sequential row cycles and data transfers.
Solution Approach 2:
The memory device performs logical operations autonomously through its integrated sensing circuitry without requiring external processing assistance. This self-service capability allows the memory to handle complex logical operations internally, reducing the need for repeated row cycles and associated power consumption.
3Device complexity
If dynamic capacitance is used for operand storage, then simple storage is achieved, but processing efficiency decreases
Solution Approach 1:
The patent replaces dynamic capacitance-based storage with a more efficient storage mechanism in the sensing circuitry. This substitution enables faster data access and manipulation, improving processing efficiency while maintaining the ability to store operands for logical operations.
Data Source
AI summary
The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.