Sense Amplifier Segmentation for Multi-State Memory Sensing
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Solution Overview
Problem
Current memory devices with integrated variable resistance memory elements face challenges in efficiently storing and retrieving data due to limitations in selector states and processing capacity, particularly in distinguishing between multiple resistance states of memory elements.
Innovation Solution
A memory device configuration with a plurality of memory cells, each having a memory element with at least three resistance states and a selector coupled in parallel, along with a sense amplifier that compares bit line voltages to reference voltages to sense data, allowing for improved data storage and retrieval by utilizing operational amplifiers, voltage detection circuits, and latch circuits to determine resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single sense circuit is used to sense bit line voltage, then the device complexity is reduced, but the measurement precision and processing capacity for distinguishing multiple resistance states deteriorates
Solution Approach 1:
The sense amplifier is divided into multiple independent sense circuits (first sense circuit and second sense circuit), each capable of independently sensing the bit line voltage. This segmentation allows parallel processing of voltage information, improving the precision of resistance state discrimination while maintaining manageable device complexity through modular architecture
Solution Approach 2:
Each sense circuit is designed with multi-functionality to handle different sensing operations. The sense circuits can independently perform voltage sensing and can be selectively activated based on the specific resistance state discrimination requirements, making the overall system versatile in handling various memory cell configurations and read operations
2Measurement precision
If multiple sense circuits are used to improve data sensing accuracy, then the measurement precision improves, but the device complexity increases
Solution Approach 1:
Multiple sense circuits are merged into a unified sense amplifier structure that shares common control logic and output processing pathways. The first and second sense circuits are combined such that their outputs are integrated through shared latch circuits and control mechanisms, achieving high measurement precision while reducing the overall device complexity compared to completely independent sense amplifiers
Solution Approach 2:
The sense amplifier employs dynamic control mechanisms where the plurality of sense circuits are selectively activated based on the specific sensing requirements. The control circuit dynamically enables or disables individual sense circuits depending on the memory cell state and read operation type, optimizing the balance between measurement precision and device complexity by activating only the necessary circuits for each operation
Data Source
AI summary
According to one embodiment, a memory device includes: a plurality of memory cells stacked in a first direction orthogonal to a substrate and each including a memory element having at least three resistance states and a selector coupled in parallel to the memory element; a bit line electrically coupled to the memory cells and extending in a second direction intersecting the first direction; and a sense amplifier configured to compare a voltage of the bit line with a plurality of reference voltages and sense data stored in the memory cells.