Sense Amplifier Offset Compensation via Segmented Bit Line Biasing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The performance of semiconductor memory is adversely affected by transistor mismatch in sense amplifiers, leading to offset noise that can result in incorrect data reading due to differences in threshold voltages and manufacturing processes.
Innovation Solution
A sense amplifier design that includes an amplification module and a control module, configuring different diode, current mirror, and inverter structures for each bit line to compensate for offset noise by adjusting voltages, thereby improving data reading accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the same two MOSFETs are used in the sense amplifier, then the device complexity is reduced, but transistor mismatch occurs due to process and temperature variation, causing offset noise that affects memory performance
Solution Approach 1:
The sense amplifier is divided into multiple independent transistor pairs (first PMOS-NMOS pair and second PMOS-NMOS pair) with separate biasing paths. Each pair operates independently to read from different bit lines, preventing mismatch-induced offset noise from affecting the entire amplifier. This segmentation allows each transistor pair to be optimized separately while maintaining overall system reliability.
Solution Approach 2:
Different biasing conditions are applied to different transistor pairs within the same sense amplifier. The first PMOS transistor receives a first bias voltage while the second PMOS transistor receives a second bias voltage, creating locally optimized operating conditions for each transistor pair. This local quality adjustment compensates for process variations and temperature effects that would otherwise cause mismatch.
2Reliability
If transistor mismatch is compensated using traditional methods, then offset noise is reduced, but the sense amplifier structure becomes more complex with additional compensation circuits
Solution Approach 1:
The control module serves multiple functions: it selectively activates different transistor pairs based on which bit line requires reading, applies appropriate bias voltages to each pair, and manages the overall read operation timing. This multi-functionality eliminates the need for separate dedicated compensation circuits, achieving offset noise reduction without increasing overall device complexity.
Solution Approach 2:
The bias voltages applied to the PMOS transistors are dynamically adjusted based on operational requirements. By changing the bias voltage parameters (first bias voltage for first PMOS, second bias voltage for second PMOS), the sense amplifier adapts to different reading scenarios and compensates for offset noise without requiring additional hardware structures.
Data Source
AI summary
A sense amplifier includes an amplification module and a control module electrically connected to the amplification module. Herein, in a case of reading a data in a memory cell on a first bit line, at an offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first diode structure, a first current mirror structure, and a first inverter with an input terminal and an output terminal connected to each other. In a case of reading a data in a memory cell on a second bit line, at the offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a second diode structure, a second current mirror structure, and a second inverter with an input terminal and an output terminal connected to each other.