Sense Amplifier Layout With Shared Active Regions Under COAG Limits
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Solution Overview
Problem
The design of sense amplifiers for DRAM integrated circuit devices faces challenges due to restrictions such as the COAG prohibition, requiring parallel fins and perpendicular gate materials, which increase chip area and limit scaling, especially in non-rotated and rotated configurations.
Innovation Solution
The implementation of hybrid rotated sense amplifier configurations, where cross-coupled pairs of transistors share a continuous active material, and gate material lines are shared between transistors, reducing the chip area penalty and allowing for shared diffusion and interconnect benefits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sense amplifier control transistors are designed with separate active materials and perpendicular gate materials to satisfy COAG prohibition, then manufacturing compliance is improved, but chip area consumption increases
Solution Approach 1:
The patent merges the active materials of sense amplifier control transistors with cross-coupled pair transistors into a continuous active material structure. This allows both transistor types to share the same active material region, reducing overall area while maintaining COAG prohibition compliance through proper gate material orientation and isolation.
Solution Approach 2:
The continuous active material serves multiple functions: it acts as the active region for both sense amplifier control transistors and cross-coupled pair transistors. This multi-functional use of the active material reduces the total area required for the sense amplifier circuit while maintaining proper electrical isolation through gate material design.
2Area of stationary object
If minimum pitch and spacing are used to reduce chip area, then device scaling is improved, but design constraint compliance deteriorates
Solution Approach 1:
By merging the active materials of different transistor types into a continuous structure, the patent reduces the number of separate active regions required, thereby minimizing pitch and spacing requirements while maintaining design rule compliance.
Solution Approach 2:
The patent resolves area constraints by transitioning from a two-dimensional layout of separate active regions to a shared continuous active material structure, effectively utilizing the vertical dimension and gate material orientation to maintain compliance while reducing footprint.
3Area of stationary object
If gate material lines are shared between transistors, then area consumption is reduced, but electrical isolation requirements become more stringent
Solution Approach 1:
The patent combines gate material lines for sense amplifier control transistors and cross-coupled pair transistors into shared interconnect structures, reducing area while maintaining proper electrical isolation through the continuous active material design and appropriate diffusion barrier implementation.
Solution Approach 2:
The continuous active material acts as an intermediary structure that allows shared gate material lines while maintaining electrical isolation between different transistor functions. The active material region, combined with diffusion barriers, provides the necessary isolation mechanism for shared interconnects.
Data Source
AI summary
Sense amplifier layout designs and related apparatuses and methods. An apparatus includes a cross-coupled pair of pull-up transistors of a sense amplifier, a cross-coupled pair of pull-down transistors of the sense amplifier, and a pair of conductive lines electrically connecting the cross-coupled pair of pull-up transistors to the cross-coupled pair of pull-down transistors. The apparatus also includes a sense amplifier control transistors sharing a continuous active material with one of the cross-coupled pair of pull-up transistors or the cross-coupled pair of pull-down transistors. A method includes asserting a shared control gate terminal of sense amplifier control transistors sharing a continuous active material with the cross-coupled pair of pull-down transistors, applying a pre-charge voltage potential to the pair of conductive lines, electrically connecting memory cells to the pre-charged pair of bit lines, and amplifying electrical charges delivered to the pair of bit lines by the memory cells.