Sense Amplifier Offset Cancellation via Shared Impurity Regions
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Solution Overview
Problem
As electronic products require miniaturization and high-capacity integrated circuit devices, the reduction in feature size of memory devices leads to threshold voltage deviations and offset noise in sense amplifiers, affecting their electrical characteristics.
Innovation Solution
The integrated circuit device incorporates a sense amplifier unit connected to a bit line and a complementary bit line, featuring a first PMOS transistor and a first NMOS transistor, along with an offset canceling unit that includes a transistor sharing a common impurity region with the NMOS transistor, to sense voltage changes and adjust voltages, thereby reducing threshold voltage deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the feature size of memory devices is reduced to achieve miniaturization and high-capacity integration, then the degree of integration increases, but threshold voltage deviation and offset noise occur in sense amplifiers
Solution Approach 1:
The patent applies local quality by creating an asymmetric transistor structure where impurity regions are selectively positioned only on one side of the gate pattern rather than symmetrically on both sides. This local modification of the doping structure compensates for threshold voltage deviations caused by miniaturization while maintaining the reduced feature size for high integration density.
2Quantity of substance
If the feature size of memory devices is reduced to achieve miniaturization, then device capacity increases, but offset noise in sense amplifiers increases
Solution Approach 1:
The asymmetric impurity region configuration locally modifies the electrical characteristics of the sense amplifier transistors. By positioning impurity regions only on one side of the gate, the structure compensates for offset noise effects while preserving the miniaturized device dimensions that enable increased capacity.
3Ease of manufacture
If conventional symmetric transistor structures are used in miniaturized devices, then manufacturing is simpler, but threshold voltage deviation occurs
Solution Approach 1:
The patent introduces a locally modified asymmetric structure that, while slightly more complex than symmetric designs, provides precise threshold voltage control. The selective impurity region placement on one side of the gate pattern enables fine-tuned electrical characteristics that compensate for miniaturization effects.
Solution Approach 2:
The patent directly applies asymmetry by configuring impurity regions to exist only on one side of the gate pattern rather than symmetrically on both sides. This asymmetric doping structure is specifically designed to counteract threshold voltage deviations that arise in miniaturized devices, achieving better voltage uniformity across the array.
Data Source
AI summary
An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.