Differential Sense Amplifier Using Shared Pass-Gate Transistors
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Solution Overview
Problem
Conventional sense amplifiers in semiconductor memories consume significant area and increase fabrication costs due to their complex structure, which includes switch transistors and dedicated pass-gate transistors, making them inefficient in terms of space and economics.
Innovation Solution
A differential sense amplifier design that eliminates switch transistors and dedicated pass-gate transistors by using multigate transistors with independent control gates, fabricated in Semiconductor-On-Insulator (SeOI) technology, which reduces the area consumption and improves efficiency by directly connecting transistors to global bit lines, thereby simplifying the circuit and reducing the number of transistors required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sense amplifier structure with switch transistors and dedicated pass-gate transistors is used, then data sensing and writing operations can be performed, but area consumption increases and fabrication costs increase
Solution Approach 1:
The patent merges the functions of dedicated pass-gate transistors into the existing pull-up and pull-down transistors of the CMOS inverters. The pull-up transistors serve dual purposes: as pull-up devices for the inverter operation and as pass-gate transistors for connecting bit lines to global bit lines. Similarly, pull-down transistors function as both inverter pull-down devices and pass-gate transistors for data writing operations. This functional merging eliminates the need for separate dedicated pass-gate transistors, thereby reducing area consumption while maintaining data sensing and writing capabilities.
Solution Approach 2:
The patent implements multi-functionality by designing the pull-up and pull-down transistors to perform multiple operations. These transistors serve as active elements for inverter operation during sensing phases and as pass-gate transistors during write operations. The universal design allows the same transistor structures to be utilized for different functional requirements (sensing, amplification, and data writing), optimizing area utilization and reducing the total transistor count in the sense amplifier circuit.
2Reliability
If conventional sense amplifier structure with switch transistors and dedicated pass-gate transistors is used, then data sensing and writing operations can be performed, but fabrication costs increase
Solution Approach 1:
The patent combines the functions of dedicated pass-gate transistors into the existing pull-up and pull-down transistors, reducing the total transistor count from eleven to fewer devices. This merging approach simplifies the circuit structure, reduces manufacturing complexity, and lowers fabrication costs while preserving the ability to perform data writing operations through the multi-functional transistor design.
Solution Approach 2:
By designing transistors with universal functionality that serves both inverter operation and pass-gate operations, the patent reduces the number of distinct transistor types and configurations required. This universality simplifies the fabrication process, reduces manufacturing variability, and lowers overall fabrication costs while maintaining reliable data writing capabilities.
3Reliability
If conventional sense amplifier structure is used, then data sensing can be performed, but device complexity increases
Solution Approach 1:
The patent merges the functions of dedicated pass-gate transistors into the existing pull-up and pull-down transistors, eliminating redundant components. This functional integration simplifies the overall circuit structure, reduces the number of interconnections required, and lowers device complexity while maintaining effective data sensing operations through the multi-functional transistor design.
Data Source
AI summary
A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-down transistors.