Sense Amplifier Sleep State for Leakage Reduction
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Solution Overview
Problem
Traditional SRAM sense amplifiers face challenges in simultaneously reducing asymmetric aging and leakage current, as they either experience bias mismatch due to asymmetric aging when idle or incur high leakage when precharged.
Innovation Solution
A sense amplifier circuit with a sleep state that shorts together the sense amplifier true and complement signal lines during idle, using a transmission gate formed by PMOS and NMOS transistors to maintain equal biasing and reduce leakage by disabling precharge and equalization during idle periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sense amplifier remains in precharge during idle, then symmetric biasing is maintained to reduce asymmetric aging, but leakage current increases due to leakage paths through precharge transistors and bitlines
Solution Approach 1:
The patent introduces a dynamic sleep state that transitions the sense amplifier between active and idle modes. During idle, the sleep circuit shorts the sense amplifier inputs together while disabling precharge, creating a dynamic configuration that maintains symmetric biasing without the leakage paths of continuous precharge operation
Solution Approach 2:
The sleep circuit acts as an intermediary mechanism that mediates between the conflicting requirements of symmetric biasing and leakage reduction. By introducing this intermediate circuit, the patent enables the sense amplifier to achieve both goals without requiring fundamental changes to the core amplifier structure
2Loss of energy
If the sense amplifier is disabled during idle, then leakage current is reduced, but asymmetric biasing occurs causing threshold voltage shift and aging mismatch
Solution Approach 1:
The sleep circuit creates an equipotential condition by shorting the sense amplifier inputs (SAT and SAC) together during idle. This ensures both inputs are at the same voltage potential, maintaining symmetric biasing across the matched transistors and preventing asymmetric aging, while still allowing the amplifier to be disabled for leakage reduction
3Loss of energy
If high threshold devices are used to reduce leakage, then leakage current decreases, but the operation speed of SRAM slows down
Solution Approach 1:
The patent employs dynamic control of the sense amplifier state rather than relying on static device parameter changes. By using the sleep circuit to dynamically transition between states, the system achieves low leakage during idle without requiring high threshold devices that would permanently slow down operation during active states
Data Source
AI summary
A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.