Sense Amplifier Architecture for Small Swing Voltage Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems face inefficiencies in sensing operations, particularly in multi-state memory devices, where determining the data state of a memory cell involves multiple sensing operations, leading to slower performance due to the need to differentiate between small voltage swings of ON and OFF memory cells.
Innovation Solution
A sense amplifier architecture is introduced that includes a sensing capacitor connected to an internal bit line through a selection switch and a latch with a pair of inverters, allowing for amplification of small voltage swings, thereby reducing sensing times. This architecture pre-charges the latch and bit line, then discharges based on the conductivity of the selected memory cell, amplifying and latching the voltage result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional sense amplifier architecture is used, then the sensing operation can be performed, but the sensing time is long due to the need to differentiate small voltage swings between ON and OFF memory cells
Solution Approach 1:
The sense amplifier performs preliminary actions by pre-charging the bit line and latch to a predetermined voltage level before the sensing operation. This preliminary preparation enables the circuit to quickly respond to small voltage swings from memory cells, reducing sensing time while maintaining the precision needed to differentiate between ON and OFF states
Solution Approach 2:
The sense amplifier architecture is segmented into distinct functional blocks including a sensing capacitor, a latch with cross-coupled inverters, and pre-charge circuits. This segmentation allows each component to be optimized for its specific function - the pre-charge circuit prepares the voltage level, the sensing capacitor captures the voltage swing, and the latch amplifies and latches the signal, collectively improving sensing speed without sacrificing precision
2Measurement precision
If multiple sensing operations are performed to determine data state in multi-state memory devices, then accurate data reading is achieved, but the overall operation time increases
Solution Approach 1:
The sense amplifier performs preliminary actions by pre-charging the bit line and latch to a predetermined voltage level before the sensing operation. This preliminary preparation enables the circuit to quickly respond to small voltage swings from memory cells, reducing sensing time while maintaining the precision needed to differentiate between ON and OFF states
Solution Approach 2:
The latch uses cross-coupled inverters that provide positive feedback to maintain and amplify the sensed voltage state. This feedback mechanism allows the circuit to quickly stabilize the sensed signal and maintain it for subsequent processing, reducing the time required for accurate data state determination in multi-state memory devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed sense amplifier architecture significantly reduces sensing times by effectively differentiating between ON and OFF memory cells with smaller voltage swings, enhancing memory performance by allowing faster data read and verify operations.
Implementation Method 1
A sensing capacitor is connected to an internal bit line that is connectable to each of one or more bit lines
Implementation Method 2
The first inverter of the latch is configured to have a gain of more than unity so that a voltage level on its input is amplified
Data Source
AI summary
A sense amplifier architecture is presented that can reduce sensing times by being able to sense smaller voltage swings between an ON memory cell and an OFF memory cell. The sense amplifier includes a sensing capacitor that, on one side, is connectable to multiple bit lines and, on the other side, to a main sense amplifier section. The main section includes a latch formed of a pair of inverters that has an input connected to the capacitor and an output that is connected to the other side of the capacitor by a third inverter. To pre-charge the latch, the input and output nodes are shorted and then the capacitor is connected to discharge the capacitor through a selected memory cell based on whether it is ON or OFF. A programming data latch for each bit line can bias the bit line to either a program enable or program inhibit level.