Sense Amplifier Split Capacitors Ferroelectric Memory Read Accuracy
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Solution Overview
Problem
Ferroelectric memory devices face challenges in achieving accurate read operations due to the trade-off between the size of the amplifier capacitor, which affects the sense window and the reliability of determining stored logic states, with larger capacitors providing efficient boosting but smaller capacitors offering better fidelity for polar charges.
Innovation Solution
The use of split capacitors in a sense amplifier, which can provide different capacitances during various portions of a read operation, allowing for a larger sense window and improved accuracy by independently coupling and decoupling the boost and integrator capacitors with a voltage source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a larger amplifier capacitor is used, then boosting efficiency is improved, but fidelity for polar charges deteriorates
Solution Approach 1:
The amplifier capacitor is divided into two separate capacitors: a first capacitor dedicated to boosting operations and a second capacitor dedicated to integrating polar charges. This segmentation allows each capacitor to be optimized for its specific function, resolving the contradiction between boosting efficiency and polar charge fidelity.
Solution Approach 2:
The circuit dynamically switches between using the first capacitor for boosting and the second capacitor for integration based on the operational phase. During the boost phase, the first capacitor is coupled to provide large capacitance for efficient boosting; during the integration phase, the second capacitor is coupled to provide appropriate capacitance for accurate polar charge integration.
2Measurement precision
If a smaller amplifier capacitor is used, then fidelity for polar charges is improved, but sense window size deteriorates
Solution Approach 1:
By separating the amplifier capacitor into two distinct capacitors, the patent enables the second capacitor to be optimized specifically for polar charge integration with appropriate capacitance value, achieving high fidelity without compromising the sense window size that is maintained by the first capacitor during boosting.
3Device complexity
If a single amplifier capacitor is used, then device complexity is reduced, but read operation accuracy deteriorates
Solution Approach 1:
The patent divides the single amplifier capacitor into two separate capacitors with distinct functions, enabling independent optimization for both boosting and polar charge integration, thereby improving read operation accuracy while maintaining manageable device complexity through clear functional separation.
Solution Approach 2:
The circuit employs dynamic switching between the first and second capacitors based on operational requirements, allowing the system to achieve high read accuracy by using the appropriate capacitor for each phase without requiring a permanently complex configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and accuracy of read operations by managing the displacement and polar charges effectively, providing a larger sense window and improving the fidelity of determining stored logic states in ferroelectric memory devices.
Implementation Method 1
coupling a first capacitor with a voltage source and a signal node
Implementation Method 2
coupling the second capacitor with the signal node
Data Source
AI summary
Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.