Sense Amplifier Split-Stack Architecture for Low-Amplitude Signal Processing
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Solution Overview
Problem
Modern semiconductor chips face challenges in extracting data from low-amplitude electrical signals due to increasing data rates, which affects processing speed and signal transmission efficiency.
Innovation Solution
A sampling circuit with increased headroom is implemented, featuring a split-stack architecture that separates the pre-charge and sense/evaluation portions into two separate stacks, utilizing a pair of input signal transistors connected via cross-coupled state nodes and a tail transistor to amplify differential signals, allowing for improved voltage regeneration and circuit speed at low power supply levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If signals are transmitted at low amplitude levels for high-speed signal transmission, then processing speed is improved, but signal extraction becomes more challenging
Solution Approach 1:
The sense amplifier circuit is divided into two separate stacks: a first stack containing the differential pair transistors for signal amplification, and a second stack containing the current source transistors. This segmentation allows independent optimization of each stack, enabling the differential pair to operate at lower voltage levels while maintaining sufficient amplification capability for low-amplitude signals.
Solution Approach 2:
The patent changes the voltage operating parameters by using separate stacks with different voltage requirements. The first stack operates at lower voltage levels suitable for amplifying small differential signals, while the second stack provides the necessary current at appropriate voltage levels, effectively decoupling the voltage requirements and enabling low-amplitude signal processing.
2Device complexity
If a single-stack sense amplifier is used, then device complexity is reduced, but headroom is limited
Solution Approach 1:
The sense amplifier is segmented into two functional stacks with distinct roles. The first stack (differential pair) is optimized for signal amplification with appropriate transistors and connections, while the second stack (current source) is optimized for providing stable bias current. This segmentation increases headroom by allowing each stack to operate at its optimal voltage level independently.
Solution Approach 2:
The patent transitions from a single-dimensional (single-stack) architecture to a two-dimensional (dual-stack) architecture, where each stack operates in a different voltage dimension. This allows the circuit to achieve greater headroom by stacking the functional blocks vertically in the circuit topology, effectively utilizing the voltage dimension to separate amplification and current sourcing functions.
3Productivity
If clock speeds are increased for faster signal processing, then productivity is improved, but power consumption increases
Solution Approach 1:
The dual-stack architecture changes the voltage and current parameters independently for each functional block. By providing stable bias current through the second stack and optimizing the voltage levels in the first stack, the circuit achieves better signal-to-noise ratio and faster convergence at lower power levels, enabling higher clock speeds without proportional power increases.
Solution Approach 2:
The sense amplifier operates in periodic cycles synchronized with the clock signal, using the stable bias current from the second stack to rapidly amplify differential signals during each clock period. This periodic operation at optimized voltage levels enables high-speed processing while maintaining lower average power consumption compared to continuous high-power operation.
Data Source
AI summary
Systems, apparatuses, and methods for implementing a sampling circuit with increased headroom are disclosed. A sampling circuit includes at least a pair of input signal transistors connected via their drains to a cross-coupled pair of state nodes. The cross-coupled pair of state nodes are coupled to a tail transistor device via the sources of N-type transistors. When clock goes low, the circuit precharges the cross-coupled pair of state nodes while simultaneously attempting to amplify the difference between the pair of input signals. The amplification is performed by a pair of transistors in series between a source of each input signal transistor and ground. Each gate of the pair of transistors is connected to an inverted clock signal. When clock goes high, the circuit stops precharging and a voltage difference between the pair of input signals is regenerated to create a resulting differential voltage on the pair of state nodes.