Sense Amplifier SRAM Cache for Smaller, Lower-Latency Memory
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Solution Overview
Problem
Memory devices with multiple memory resources, such as SRAM and DRAM arrays, face increased physical size, resource consumption, and latency due to the inclusion of separate SRAM arrays, which are often underutilized.
Innovation Solution
Utilize sense amplifiers coupled to a DRAM array as a SRAM resource, effectively replacing the need for a separate SRAM array by using them as a SRAM cache when idle, and transferring data during memory array refreshes to preserve data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate SRAM array is included in the memory device, then SRAM cache functionality is provided, but the physical size of the memory device increases
Solution Approach 1:
The sense amplifiers are designed to perform multiple functions: during normal operation they sense data from the DRAM array, and during idle periods they function as SRAM cache storage. This multi-functionality eliminates the need for a separate SRAM array, reducing the overall memory device area while maintaining SRAM cache capabilities.
Solution Approach 2:
The sense amplifiers serve themselves by utilizing their idle time to provide SRAM cache functionality. Instead of remaining inactive during certain operation modes, they autonomously function as cache memory, thereby providing additional functionality without requiring external resources or increasing device area.
2Adaptability or versatility
If a separate SRAM array is included in the memory device, then SRAM cache functionality is provided, but resource consumption increases
Solution Approach 1:
The sense amplifiers are designed to perform multiple functions: during normal operation they sense data from the DRAM array, and during idle periods they function as SRAM cache storage. This multi-functionality eliminates the need for a separate SRAM array, reducing the overall memory device area while maintaining SRAM cache capabilities.
Solution Approach 2:
The sense amplifiers serve themselves by utilizing their idle time to provide SRAM cache functionality. Instead of remaining inactive during certain operation modes, they autonomously function as cache memory, thereby providing additional functionality without requiring external resources or increasing device area.
3Adaptability or versatility
If a separate SRAM array is included in the memory device, then SRAM cache functionality is provided, but latency increases
Solution Approach 1:
The invention extracts the SRAM cache functionality from a separate physical array and integrates it into the existing sense amplifier circuitry. By taking out the cache function and embedding it within the sense amplifiers, the system eliminates the need for data transfer between separate SRAM and DRAM arrays, thereby reducing access latency.
Solution Approach 2:
The sense amplifiers and SRAM cache functionality are merged into a single integrated unit. This combination allows the cache operations to be performed directly within the sense amplifier circuitry without requiring additional data movement between separate memory arrays, thus reducing overall access time and latency.
4Area of stationary object
If sense amplifiers are used as SRAM cache, then memory device size is reduced, but data integrity during refresh operations may be compromised
Solution Approach 1:
Before the DRAM array undergoes refresh operations, the controller identifies which sense amplifiers are idle and pre-prepares them to receive data from the array rows that will be refreshed. This preliminary arrangement ensures that data can be quickly restored to the sense amplifier cache after refresh, maintaining data integrity without compromising the space-saving benefits.
Solution Approach 2:
The controller acts as an intermediary that coordinates between the DRAM array refresh operations and the sense amplifier cache. It manages the temporary data movement and ensures that data is preserved and restored correctly, thereby maintaining reliability while enabling the sense amplifiers to function as cache memory during refresh cycles.
Data Source
AI summary
Methods, systems, and devices related to sense amplifiers of a memory device serving as a Static Random Access Memory (SRAM) cache. For example, a memory array can be coupled to sense amplifiers. In a first mode, the sense amplifiers can be electrically disconnect from digit lines of the memory array. In the first mode, data and metadata of a cache line can be stored in the sense amplifiers when electrically disconnected from the number of digit lines. In the first mode, a portion of the data can be communicated, based on the metadata, from the sense amplifiers to the processing device. In a second mode, the sense amplifiers can connect to the memory array and sense data from the memory array.