Sense Amplifier Flip-Flop With Cross Transfer for Stable Latching

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Solution Overview

Problem

Existing flip-flop designs face challenges such as insufficient setup time, sensitivity to clock skew, and high power consumption, particularly in high-speed digital systems, with sense amplifier-based flip-flops experiencing data acquisition errors due to charge/discharge nodes.

Innovation Solution

A sense amplifier circuit with a charge module and a sense module, featuring cross-connected amplification circuits and transfer circuits that maintain signal states during differential input signal hopping, ensuring stable data latching and low power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a transmission gate flip-flop is used, then the flip-flop can be switched between two stable states, but the setup time is insufficient and data cannot be stably latched

Engineering Contradiction:
Improvedata latching stabilityVSAvoidsetup time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The flip-flop is divided into master and slave levels with separate clock phases. The master latch captures data during one clock phase while the slave latch prepares to receive, allowing overlapping operations that reduce critical path delay and improve setup time without compromising latching stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The slave latch is pre-charged to a known state before data transfer. This preliminary action ensures that when data is transferred from the master latch, the slave latch is ready to accept and stabilize the data, reducing the required setup time while maintaining reliable latching.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If a pulse triggered flip-flop is used, then the setup time requirement is improved, but an extra circuit is needed to generate a clock tree, increasing power consumption and area overhead

Engineering Contradiction:
Improvesetup timeVSAvoidpower consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The flip-flop uses periodic clock phases (first and second non-overlapping clock signals) to control data transfer between master and slave latches. This periodic action provides well-defined setup and hold windows without requiring complex pulse generation circuits, reducing power consumption and area while maintaining improved setup time characteristics.

Inventive Principle:
Principle #19Periodic action

3Loss of time

If a sense amplifier-based flip-flop is used, then setup time and hold time are reduced, but there are many charge/discharge nodes that lead to data acquisition errors

Engineering Contradiction:
Improvesetup time and hold timeVSAvoiddata acquisition accuracy
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent removes the problematic charge/discharge nodes from the sense amplifier circuit while retaining the essential differential sensing functionality. By extracting these unstable nodes and replacing them with a more stable master-slave latch structure using non-overlapping clocks, the design achieves fast setup/hold times without the data acquisition errors caused by charge/discharge node instability.

Inventive Principle:
Principle #2Taking out (Extraction)

4Productivity

If a semi-dynamic flip-flop is used, then the D-Q delay is short, but the circuit cannot tolerate clock skew and time borrowing

Engineering Contradiction:
ImproveD-Q delayVSAvoidclock skew tolerance
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The flip-flop uses dynamic clocking with non-overlapping clock phases that allow flexible timing relationships. The master and slave latches operate in different clock phases, enabling the circuit to tolerate clock skew between different parts of the system and allowing time borrowing across clock boundaries while maintaining short D-Q delay through efficient data transfer during active clock phases.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11979121B2Sense amplifier circuit and flip-flop
Publication Date: 2024.05.07 CHANGXIN MEMORY TECH INC
  • US11979121B2 patent drawing
  • US11979121B2 patent drawing
  • US11979121B2 patent drawing

AI summary

A sense amplifier circuit includes: a charge module configured to charge a set signal node and a reset signal node according to a clock signal; and a sense module configured to sense and amplify a differential input signal according to the clock signal; where, the sense module includes a first amplification circuit, a second amplification circuit, and a cross hopping transfer circuit cross-connected between the first amplification circuit and the second amplification circuit. The cross hopping transfer circuit is configured to transfer a valid signal of a newly started amplification circuit to another amplification circuit if sensing is completed and the differential input signal hops, such that a set signal/reset signal remains unchanged. A flip-flop includes the sense amplifier circuit.