Sense Amplifier Flip-Flop Staging for Process Variation Tolerance
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Solution Overview
Problem
Conventional sense amplifier flop designs are prone to malfunction due to process variation, requiring a tightly controlled conductivity ratio between N-FETs and P-FETs, leading to costly yield loss and fabrication expenses.
Innovation Solution
A process variation tolerant sense amplifier flip-flop circuit design with a differential subsystem that eliminates short-circuit currents by staging transitions, reducing the need for tight control over N-FET versus P-FET conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional differential sense amplifier flop design is used, then circuit efficiency and functionality are improved, but process variation tolerance deteriorates due to sensitivity to conductivity ratio variations between N-FETs and P-FETs
Solution Approach 1:
The circuit is divided into separate pull-up and pull-down subsystems with independent control mechanisms. The pull-up network uses P-FETs while the pull-down network uses N-FETs, allowing each subsystem to be optimized and controlled independently, thereby eliminating the need for tight matching between complementary transistors.
Solution Approach 2:
The control subsystem generates delayed representations of input data signals in advance to pre-coordinate the switching actions of pull-up and pull-down paths. This preliminary timing adjustment ensures that transitions are staged properly, preventing simultaneous conduction and eliminating short-circuit currents before they can occur.
2Reliability
If tight process variation control is implemented to ensure sense amplifier flop functionality, then reliability is improved, but manufacturing cost and yield loss increase
Solution Approach 1:
The invention changes the operational parameters of the sense amplifier flop by introducing independent control of pull-up and pull-down networks through delayed signal representations. This parameter change allows the circuit to function correctly across a broader range of process variations without requiring tight manufacturing control.
3Area of stationary object
If conventional differential structure is used in sense amplifier flop, then circuit compactness is improved, but short-circuit currents occur during transitions due to uncoordinated N-FET and P-FET switching
Solution Approach 1:
The control subsystem prepares delayed representations of input signals in advance to pre-coordinate the switching timing of pull-up and pull-down paths. This preliminary timing adjustment ensures that transitions are staged properly, preventing simultaneous conduction and eliminating short-circuit currents before they can occur.
Solution Approach 2:
The control subsystem acts as an intermediary between the input signals and the pull-up/pull-down networks, introducing delayed representations that mediate the timing of transitions. This intermediary control ensures that one path is fully established before the other is activated, preventing direct short-circuit currents while maintaining compact differential structure.
Data Source
AI summary
One embodiment of the present invention sets forth a sense amplifier flop design that is tolerant of process variation. Specific staging of signal transitions through the sense amplifier flop circuit eliminate operational phases involving short-circuit currents between n-channel field-effect transistors (N-FETs) and p-channel field effect transistors (P-FETs) in a complementary-symmetry metal-oxide semiconductor process. By eliminating short-circuit currents between N-FETs and P-FETs within the sense amplifier flop, a large variation in conductivity ratio between N-FETs and P-FETs may be tolerated by the sense amplifier flop. This tolerance to conductivity ratio translates to a tolerance for process variation by the sense amplifier flop circuit.