Bit-line Sense Amplifier Switching for DRAM Refresh Power Reduction
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face high power consumption during refresh operations, which is a significant challenge for mobile devices, as existing technologies do not effectively reduce current consumption during these operations.
Innovation Solution
A semiconductor memory device with an open bit-line structure that includes a sense amplifier connected to both a bit line and a complementary bit line, with switches that electrically separate the bit lines from the sense amplifier during refresh operations, allowing current to be consumed only by the bit line or its complementary bit line, thereby reducing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both bit line and complementary bit line are connected to sense amplifier during refresh operation, then sense amplifier can amplify data from either bit line, but power consumption increases due to current flowing through both bit lines
Solution Approach 1:
The patent divides the bit line connection to the sense amplifier into two separate controllable paths: one for the bit line and another for the complementary bit line. Switches are introduced to segment the connection, allowing selective activation of only one bit line path during refresh operations, thereby reducing power consumption while maintaining the sense amplifier's capability to handle data from either bit line when needed.
2Use of energy by moving object
If switches are added to electrically separate bit line from sense amplifier, then power consumption decreases, but device complexity increases
Solution Approach 1:
The patent introduces switches as intermediary components between the bit lines and the sense amplifier. These switches act as mediators that can selectively connect or disconnect the bit lines from the sense amplifier based on operational mode (read vs. refresh), enabling power consumption reduction without permanently altering the sense amplifier's functionality or requiring complex reconfiguration circuits.
Data Source
AI summary
A semiconductor memory device is provided which includes a sense amplifier, a bit line connected to a plurality of memory cells of a first memory block, a complementary bit line connected to a plurality of memory cells of a second memory block, a first switch configured to connect the bit line to the sense amplifier, and a second switch configured to connect the complementary bit line to the sense amplifier. The first switch is configured to electrically separate the bit line from the sense amplifier when the second memory block performs a refresh operation.