Semiconductor Memory Sense Amplifier Testing via Dynamic Bit Line Switching
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Solution Overview
Problem
Current semiconductor memory apparatuses lack a method to test the characteristics of sense amplifiers, making it difficult to diagnose and address defects in memory cells, as the functionality of sense amplifiers cannot be effectively evaluated.
Innovation Solution
A semiconductor memory apparatus and method that includes a sense amplifier coupled to bit lines, a switching unit to connect bit lines to a first node during a test mode, a mode selecting unit to choose between a pad and ground terminal, and a testing unit to supply current, allowing for the evaluation of sense amplifier performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional semiconductor memory apparatus configurations are used, then the device structure remains simple, but the ability to test sense amplifier characteristics is lost
Solution Approach 1:
The patent implements dynamic functionality by enabling the bit lines to be selectively connected to different nodes based on operational mode. During test mode, the switching unit dynamically reconfigures the bit line connections to couple them to the first node, whereas during normal operation they connect to memory cells. This dynamic reconfiguration allows the same hardware to serve dual purposes: memory operation and sense amplifier testing.
Solution Approach 2:
The patent applies multi-functionality by designing the bit lines to serve multiple purposes: they function as data transmission lines during normal memory operations and as test signal pathways during test mode. The switching unit and mode selecting unit enable this universal usage, allowing the test current to flow through the bit lines and sense amplifiers without requiring separate dedicated test structures.
2Reliability
If sense amplifier testing is implemented, then defect diagnosis capability is improved, but the operational complexity increases
Solution Approach 1:
The patent implements self-service functionality where the sense amplifiers test themselves using the existing bit lines and circuit structures. The testing unit supplies current that flows through the bit lines and sense amplifiers, allowing the sense amplifiers to evaluate their own current amplification capabilities without requiring external specialized test equipment or complex external testing procedures.
Solution Approach 2:
The switching unit acts as an intermediary that facilitates the connection between the bit lines and the first node during test mode. This intermediary component enables the test current to reach the sense amplifiers through the bit lines while isolating the normal memory operation pathways, thereby simplifying the testing operation by providing a clear, controlled current path.
3Measurement precision
If bit lines are connected to first node during test mode, then sense amplifier current amplification can be measured, but normal memory operation is disrupted
Solution Approach 1:
The patent employs dynamic switching to adapt the bit line connections based on the operational mode. The mode selecting unit responds to mode selection signals to dynamically reconfigure the switching unit, connecting bit lines to the first node during test mode and to memory cells during normal operation. This dynamic adaptation allows the system to flexibly switch between testing and operational modes without hardware modifications.
Solution Approach 2:
The patent segments the operational modes into distinct test mode and normal operation mode pathways. By using the switching unit to create separate connection pathways controlled by the mode selecting unit, the system can isolate the test current pathway from the normal data operation pathway, allowing independent optimization of each mode without interfering with the other.
Data Source
AI summary
A semiconductor memory apparatus includes a sense amplifier coupled to a plurality of bit lines, a switching unit configured to cause the plurality of bit lines to be coupled to a first node in response to a switching signal, a mode selecting unit configured to selectively couple the first node to a pad or a ground terminal in response to a mode selection signal and a testing unit configured to supply current to the pad during a test mode.